Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression

1. Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression Balaji Vaidyanathan, Yuan Xie Department of CSE Pennsylvania State University, University Park PA-16801

2. Index Terms • Energy reduction • Code-compression hardware • crosstalk

3. Presentation Summary • Introduction and Motivation • Background • Energy-aware code assignment • Experimental Setup • Experimental Results • Conclusion

4. Presentation Summary • Introduction and Motivation • Background • Energy-aware code assignment • Experimental Setup • Experimental Results • Conclusion

5. Introduction and Motivation • Power aware embedded system design is necessary. • Interconnect power is a major power consumer. • Comparable to cache, memory controller, core power [1]. • Interconnect dynamic power due to • toggling (↓) with technology scaling • crosstalk (↑) with technology scaling [2] [1] Lahiri et al., CODES-ISSS’04 [2] Sotirsadis et al., ICCAD’04 Magen et al., Intel Corporation, SLIP’04

6. Introduction and Motivation A B Inter-wire or crosstalk capacitance GND L Self Capacitance W CA_to_B L.T T H α CB_to_GND L.W S

7. Introduction and Motivation A B L GND W 2T CA_to_B 2.(L.T) H α CB_to_GND L.W S

8. Introduction and Motivation CA_to_B λ. (L.T) α CB_to_GND L.W 1.742 in 250nm 9.82 in 70nm Inter-wire coupling capacitance will dominate total interconnect capacitance in future technologies.

9. Introduction and Motivation • Code compression reduces code size and power. • But increases entropy. • Is there a compression scheme that can be utilized to reduce interconnect power ? • Variable-to-Fixed (V2F) compression scheme (explained later) • Tunstall introduced V2F coding • Xie et al. used it to reduce code size and interconnect toggle power (not crosstalk induced power).

10. Presentation Summary • Introduction and Motivation • Background • Energy-aware code assignment • Experimental Setup • Experimental Results • Conclusion

11. W i d t h 0 [C2,W2] [C3,W3] [C1,W1] 1 3 0 2 0.2 1 3 0 2 0.2 0.8 0.8 6 4 [C4,W4] [C5,W5] [C6,W6] D e p t h 5 7 4 6 0.3 D e p t h 5 7 4 6 0.3 0.6 0.4 0.7 2 bit 0.7 10 8 0.9 9 11 8 10 9 11 8 10 0.9 0.1 0.1 14 12 13 15 12 14 13 15 12 14 2 2 1 3 0 0 3 1 2 2 1 3 0 0 3 1 Background Markov V2F code compression Xie et al., ISSS-CODES ‘02. [C0,W0]

12. [C2,W2] [C3,W3] [C1,W1] 0 1 0 1 1 1 0 1 0 0 0 0 [C4,W4] [C5,W5] [C6,W6] N bit 1 0 0 0 0 0 0 1 1 1 1 0 Background Markov V2F code compression Xie et al., ISSS-CODES ‘02. Variable length bit stream to Fixed length Codes

13. Background Markov V2F code compression • We can assign random codes • why not do a power aware assignment ? • Each code book is re-coded with power aware codes • Based on application profiling (algorithm explained later) • Note • no change in compression algorithm or its efficiency. • Only code-bit mapping changes • No h/w change required (for both compression and de-compression)

14. Background Crosstalk and Power Models Pdyn = 0.5 * Ctotal * Vdd2 * f Ctotal = Cs * Nt Wire-to-substrate/ Self capacitance Nt = Ns + λ* Nc 1.742 in 250nm 9.82 in 70nm Coupling Transition Self transition / Hamming distance Sotiriadis et al., IEEE CICC, 2000.

15. Background Crosstalk and Power Models Pdyn = Constant * Ctotal Ctotal= Self Capacitance * (Toggles + λ* Crosstalk_Transitions) = Self Capacitance * (Ns + λ* Nc)

16. Background Nt = Ns + λ* Nc Total Transition Table Head = (0000) λ = 3 = 4 = 11

17. Presentation Summary • Introduction and Motivation • Background • Energy-aware code assignment • Experimental Setup • Experimental Results • Conclusion

18. Source Code Compilation Profiling Energy-aware Compression Object Code Decompression Hardware Energy-aware code assignment Implementation flow

19. [C2,W2] [C3,W3] [C1,W1] [C4,W4] [C5,W5] [C6,W6] N bit S1 S2 1 0 1 0 1 0 0 0 A C 0 0 0 1 0 1 0 0 D B [C3,W3] [C1,W1] A [C2,W2] A2 A1 E7 E6 E1 A B [C5,W5] [C2,W2] Energy-aware code assignment • The instructions in the application are assigned dummy codeword. • Vertical and horizontal adjacency of codeword is collected from the application profile. • The codeword to be assigned are picked in pairs that are most vertically connected. • The Codeword pairs are assigned cross-talk aware binary bits. • Horizontal adjacency is used to take care of boundary conditions

20. Presentation Summary • Introduction and Motivation • Background • Energy-aware code assignment • Experimental Setup • Experimental Results • Conclusion

21. Experimental Setup • Cycle accurate TMS320C6x (Texas Instruments DSP VLIW processor) simulator. • Media benchmarks are compiled using Code Composer Studio IDE. • BPTM model for bus is used. • 4-bit length codewords are used.

22. Presentation Summary • Introduction and Motivation • Background • Energy-aware code assignment • Experimental Setup • Experimental Results • Conclusion

23. Experimental Results % contribution of inter-wire in uncompressed approach 75-95% of Interconnect dynamic power is inter-wire coupling transition ~250nm 70nm

24. Experimental Results % power reduction compared to uncompressed approach 42-68% inter-wire coupling power reduction 55-71% total dynamic power reduction using 32x32 Markov model Toggle Power ~250nm ~70nm

25. Experimental Results 225% power increase due to random codeword assignment compared to optimized case % power of random-case compared to optimized approach ~250nm ~70nm

26. Experimental Results 570-670% power increase due to worst-case codeword assignment compared to optimized case % power of worst-case compared to optimized approach ~250nm ~70nm

27. Presentation Summary • Introduction and Motivation • Background • Energy-aware code assignment • Experimental Setup • Experimental Results • Conclusion

28. Conclusion • Code compression hardware considering inter-wire coupling transition is proposed. • No extra delay, power or area overhead incurred. • 55-71% reduction in interconnect dynamic power is obtained. • 2X power reduction compared to random-case.

29. Thank You Questions?