ESL and High-level Design: Who Cares? Anmol Mathur CTO and co-founder, Calypto Design Systems

1. ESL and High-level Design: Who Cares? Anmol Mathur CTO and co-founder, Calypto Design Systems

4. Trends in Applications and Processor Design

5. Trends Driven by Consumer Electronics • Time-to-market is king! • Ability to re-target designs to new technology nodes • Ability to turn around ASICs in 3 month cycles • Flexible architectures • Allow same semiconductor part to live in multiple design generations • Low power designs • System-level and micro-architectural decisions impact power very significantly • Software is the queen! • Key differentiation in consumer products is via applications • Early software development is key

6. Optimization • Performance • Power / battery life • Design updates • Economics • Development Cost • Time to Revenue • Re-spin reduction • Complexity • Increasing design size • HW / SW co-design • Verification testbench System Level Design • Productivity • Design reuse • Platform design • Optimization Move to System-level Design Design tools to leverage system-level models for RTL design and verification are needed

7. Usage of System Level Model Functional reference model Faster Simulation Platform for software development System Level Model SLM to RTL Flows (High Level Synthesis) Architectural and Performance Analysis

8. SLM Algorithmic Manual Process RTL Micro-architecture Imp. SLM to RTL Gap Manual Process Process Flow User Control Broad Control Limited Control Broad Control

9. Greater power savings opportunities at higher levels of abstraction Greater accuracy of power analysis requires detailed layout information Accurate Switching Activity Accurate Capacitance Power Dilemma

10. Status of High-level Modeling Today • Majority of design teams still using raw C/C++ • Proprietary modeling of simulation time • Simulation speed and ease of coding are key criteria • System-model and RTL partitioning is not consistent • Hard to use system-models for RTL verification • System-level modeling and RTL teams do not talk! • Several different system models at differing levels of abstraction often exist • Different level of interface/timing accuracy • Different levels of computational accuracy • Diverse/non-standard modeling makes the space very fragmented • Very hard to build tools for verification/synthesis

11. SLM to RTL Flows Manual SLM to RTL DESIGN FLOW SLM TO RTL HLS DESIGN FLOW Algorithm Functional Description Algorithm Functional Description System Level Model Floating Point Model Floating Point Model System Designer Fixed Point Model Fixed Point C++ Model + High Level Synthesis Micro-architecture Definition Constraints RTL Synthesis Hardware Designer + Manual Methods Logic Analyzer RTL Design Place & Route Hardware ASIC/FPGA RTL Area/Timing Optimization • Replaces manual RTL creation with automation • Connects system domain to hardware design • Technology based design space exploration. • Up to 20x reduction in RTL creation Precision RTL or DC RTL Synthesis Vendor Logic Analyzer Place & Route ASIC or FPGAVendor Hardware ASIC/FPGA

12. Technology files(Standard Cells + RAM cuts) FPGANetlist FPGAsynthesis High Level Synthesis SLM to RTL Flow Target System Analysis Design model Algorithm FPGA C/C++SystemC RTL GDS2 RTL to layout ASIC Formal Proof (SEC)

13. Making ESL/HLM a Reality • Standardized levels of abstraction in system-level models • SystemC 2.0 starting to do that • Consistency between system-level models and RTL • Coherent system-level and RTL design teams • Tool eco-system to link system-level and RTL • System-level model validation • Hardware-software co-simulation • High-level synthesis • Sequential equivalence checking • Sequential/micro-architectural power optimizations at RTL and micro-architectural levels

14. www.calypto.com