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Post RTL structures/flows targeting low power

Post RTL structures/flows targeting low power. Naveen M Kumar Intel Corporation Bangalore, India. Srinivas R Jammula Intel Corporation Bangalore, India. Ambar Mukherji Intel Corporation Bangalore, India. Motivation.

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Post RTL structures/flows targeting low power

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  1. Post RTL structures/flows targeting low power Naveen M Kumar Intel Corporation Bangalore, India Srinivas R Jammula Intel Corporation Bangalore, India Ambar Mukherji Intel Corporation Bangalore, India

  2. Motivation • Power reduction is important for both high performance and battery life scenarios • Traditionally, optimization steps in the design flow prioritize Timing than Power Power focus implementation Needed

  3. Scope of work Our focus area • Our primary focus will be on synthesis to Tape-In • Addresses by choosing power friendly design structures • Complementing with new power friendly flows

  4. Tech1 :: Latch movement in memory • Moved latches from o/p to i/p of decoder • 2n latches reduced to n latches Genram latch movement [RTL] Logic Synthesis Before swap Floorplan Placement Clock Tree After swap Routing Post Route Opt Layout Finishing

  5. Tech2 :: Sequential Cluster/multi-bit Logic Synthesis • flops pulled together – reduces clock routing • Single flops intercepted as Dual/Quad flops – clocks shared Floorplan Placement Seq clustering Clock Tree merge Clock Tree split Routing Post Route Opt Layout Finishing

  6. ClkAND Clk Buffer Clk Source Tech3 :: Clocks L1/L2 swap & Low Vt Logic Synthesis • Power friendly structure by swapping the clock-AND gate • Clock-tree with low-Vt cells instead of high-Vt Floorplan L2 L2 Placement Clk And Clk Buffer Clock Tree merge Low Power L1 Medium Power Clock L1/L2 Swap High Power L1 Flops Clock Tree split Routing CTS – Before Swap CTS – After Swap Post Route Opt Layout Finishing

  7. Results • Power reduction achieved in the entire design implementation phase • Enhanced performance per watt significantly • Final quantification of all 3 techniques are tabulated below Review Your structures/Flows Carefully Make them Power friendly

  8. Summary/Next Steps • Lot of scope to improve the current EDA tools to optimize for low power • Can these optimizations parameters become part of the cost function of the tool suite? • To get more global optimal solution • There is scope for micro-architectural improvements • For ex: Clustering was effective due to native data flow • Improve the data path partitioning

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