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Fibonacci Sequence

Fibonacci Sequence. Lecture L10.1 Lab 11. Fibonacci Sequence. 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233,…. F (0) = 0 F (1) = 1 F ( n + 2) = F ( n ) + F ( n + 1) for all n ≥ 0. b a. a a + b. =. The Golden Rectangle. f =. a 2 = ab + b 2. 1 = f + f 2.

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Fibonacci Sequence

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  1. Fibonacci Sequence Lecture L10.1 Lab 11

  2. Fibonacci Sequence 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233,… F(0) = 0 F(1) = 1 F(n + 2) = F(n) + F(n + 1) for all n ≥ 0.

  3. b a a a + b = The Golden Rectangle f = a2 = ab + b2 1 = f + f2

  4. Good Fibonacci Web Site http://www.mcs.surrey.ac.uk/Personal/R.Knott/Fibonacci/fibnat.html

  5. Logic diagram to generate Fibonacci numbers

  6. reg8bit.abl MODULE reg8bit INTERFACE([D7..D0],clk,clr,set,load -> [Q7..Q0]); TITLE '_______________, __________________, ___/___/03' DECLARATIONS " Input Pins " clk PIN; " clock clr PIN; " synchronous clear set PIN; " synchronous preset load PIN; " load D7..D0 PIN; " 8-bit register input D = [D7..D0]; " Output Pins " Q7..Q0 PIN ISTYPE 'reg buffer'; " 8-bit register Q = [Q7..Q0]; " 8-bit reg. output vector

  7. reg8bit.abl (cont.) EQUATIONS Q.clk = clk; [Q7..Q1].clr = clr # set; Q0.clr = clr; Q0.set = set & !clr; Q.D = _________________; END reg8bit Note: Synchronous .clr and .set clr will set Q = [0,0,0,0,0,0,0,0] set will set Q = [0,0,0,0,0,0,0,1]

  8. fib.abl MODULE fib TITLE '__________________, __________________, ___/___/03' DECLARATIONS " Functional Blocks " adder8 INTERFACE([A7..A0],[B7..B0] -> [S7..S0]); ad1 FUNCTIONAL_BLOCK adder8; reg8bit INTERFACE([D7..D0],clk,clr,set,load -> [Q7..Q0]); R1 FUNCTIONAL_BLOCK reg8bit; W FUNCTIONAL_BLOCK reg8bit; binbcd INTERFACE([B7..B0] -> [P9..P0]); BCD1 FUNCTIONAL_BLOCK binbcd; hex7seg INTERFACE([D3..D0] -> [a,b,c,d,e,f,g]); d7L FUNCTIONAL_BLOCK hex7seg; d7R FUNCTIONAL_BLOCK hex7seg;

  9. fib.abl (cont.) " Inputs Pins " clock PIN 12; " 1 Hz clock (jumper) clear PIN 70; " pushbutton S1 " Intermediate Nodes " [P9..P0] NODE ISTYPE 'com'; Hundreds = [P9,P8]; Tens = [P7..P4]; Units = [P3..P0]; " Output Pins " LED1,LED2 PIN 32,33 ISTYPE 'com'; " LEDs 1,2 LED9..LED16 PIN 35,36,37,39,40,41,43,44 ISTYPE 'com'; RedLEDs = [LED9..LED16]; [aa,bb,cc,dd,ee,ff,gg] PIN 57,58,61,62,63,65,66 ISTYPE 'com'; " Leftmost (tens) 7-segment LED display [a,b,c,d,e,f,g,dp] PIN 15,18,23,21,19,14,17,24 ISTYPE 'com'; " Rightmost (units) 7-segment LED display

  10. fib.abl (cont.) EQUATIONS R1.clk = clock; R1.clr = 0; R1.set = clear; " preset to 1 R1.load = 1; R1.[D7..D0] = ___________; " input to R1 register ad1.[A7..A0] = ___________; " adder 'A' input ad1.[B7..B0] = ___________; " adder 'B' input W.clk = clock; W.clr = clear; " reset to 0 W.set = 0; W.load = 1; W.[D7..D0] = ___________; " input to W register

  11. fib.abl (cont.) RedLEDs = W.[Q7..Q0]; " binary Fibonacci value BCD1.[B7..B0] = W.[Q7..Q0]; " binary input to bcdbin module [P9..P0] = BCD1.[P9..P0]; " BCD output from binbcd module [LED1,LED2] = Hundreds; " BCD hundreds d7L.[D3..D0] = Tens; [aa,bb,cc,dd,ee,ff,gg] = d7L.[a,b,c,d,e,f,g]; " BCD tens d7R.[D3..D0] = Units; [a,b,c,d,e,f,g] = d7R.[a,b,c,d,e,f,g]; " BCD units dp = clock;

  12. fib.abl (cont.) test_vectors([clock,clear] -> [Hundreds,Tens,Units]) [.C.,1] -> [0,0,0]; [.C.,0] -> [__,__,__]; [.C.,0] -> [__,__,__]; [.C.,0] -> [__,__,__]; [.C.,0] -> [__,__,__]; [.C.,0] -> [__,__,__]; [.C.,0] -> [__,__,__]; [.C.,0] -> [__,__,__]; [.C.,0] -> [__,__,__]; [.C.,0] -> [__,__,__]; [.C.,0] -> [__,__,__]; [.C.,0] -> [__,__,__]; [.C.,0] -> [__,__,__]; [.C.,0] -> [__,__,__]; END fib

  13. Logic diagram to generate Fibonacci numbers

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