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Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell Process

Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell Processor. -Pham, D.C.; Aipperspach, T.; Boerstler, D.; Bolliger, M.; Chaudhry, R.; Cox, D.; Harvey, P.; Harvey, P.M.; Hofstee, H.P.;

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Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell Process

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  1. Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell Processor -Pham, D.C.; Aipperspach, T.; Boerstler, D.; Bolliger, M.; Chaudhry, R.; Cox, D.; Harvey, P.; Harvey, P.M.; Hofstee, H.P.; Johns, C.; Kahle, J.; Kameyama, A.; Keaty, J.; Masubuchi, Y.; Pham, M.; Pille, J.; Posluszny, S.; Riley, M.; Stasiak, D.L.; Suzuoki, M.; Takahashi, O.; Warnock, J.; Weitzel, S.; Wendel, D.; Yazawa, K.;Solid-State Circuits, IEEE Journal ofVolume 41,  Issue 1,  Jan. 2006 Page(s):179 - 196 Digital Object Identifier 10.1109/JSSC.2005.859896 Presented by - Rooban Venkatesh K.G.T

  2. CLOCK DISTRIBUTION OF FIRST GENERATION CELL PROCESSOR 3 clock distribution systems(with independent PLL ) for processor, bus interface, and memory interface A main high frequency clock grid covers over 85% 2nd and 3rd clock grids occupy 8 mm2 and 15 mm2, which are interleaved with the main clock grid structure, creating multiple clock frequency islands within the chip All clock grids constructed on final two layers of metal, and supported by a matrix of over 850 individually tuned buffers.

  3. CLOCK DISTRIBUTION OF FIRST GENERATION CELL PROCESSOR Three clock grids required over 1100 clock buffers and 19.4 m of metal. Wire lengths between the grid and grid buffer were reduced to achieve higher clock speed. Clock distribution power dissipation was determined by three main categories of capacitances—clock load, lower level twig and mesh wires, and grid clock buffers Clock gating were used to reduce power consumption

  4. CLOCK DISTRIBUTION OF FIRST GENERATION CELL PROCESSOR • Clock twig wires, connecting clock loads to the clock grid, had widths tuned • Wire width tuning decreased clock twig wire capacitance by as much as 42% without sacrificing local clock skew. • Lower level grid wire capacitance allowed reduction in grid buffer drive strengths. • Further reduction in grid buffer drive strength was • achieved through matching one of seven buffer drive strengths to the local grid and clock load capacitances. • These techniques lowered clock distribution power dissipation by more than 20% over previous designs Chip grid analysis shows the simulated chip clock skew to be less than 12 ps

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