ENGG3190 Logic Synthesis “Multi Level Logic” (Part I)

1. ENGG3190Logic Synthesis“Multi Level Logic”(Part I) Winter 2014 S. Areibi School of Engineering University of Guelph

2. Outline • Multi Level Synthesis: Why? • Representations • What are we going to Optimize? • How to Optimize it? • Logic Transformations • The Algebraic Model. • Algebraic Division • Obtaining factors.

3. Logic Optimization Two-level logic (PLA) Multi-level logic (standard cells) Heuristic (espresso) Exact (QM) Boolean Functional (BDD-based) Structural (SIS) Functional (AC, Kurtis) algebraic Logic Optimization methods Boolean

4. Multilevel Logic Minimization • In many applications, 2-level logic is unsuitable as compared to random (multilevel) logic. • Gates with high fanin are slow, and take more area. • It makes sense to transform a 2-level logic realization to multi-level logic. • For Multilevel logic we will need new data structures, new computational models, new math, new operators.

5. Motivation • Combinational logic circuits very often implemented as multiple-level networks of logic gates. • Provides several degrees of freedom in logic design • Exploited in optimizing area and delay. • Different timing requirements on input/output paths. • Multiple-level networks viewed as interconnection of single-output gates • Single type of gate (e.g. NANDs or NORs). • Instances of a cell library. • Macro cells. • Multilevel optimization is divided into two tasks • Optimization neglecting implementation constraints assuming loose models of area and delay. • Constraints on the usable gates are taken into account during optimization.

6. Network Optimization • Two-level logic • Area and delay proportional to cover size. • Achieving minimum (or irredundant) covers corresponds to optimizing area and speed. • Achieving irredundant cover corresponds to maximizing testability. • Multiple-level logic • Minimal-area implementations do not correspond in general to minimum-delay implementations and vice versa. • Minimize area (power) estimate • subject to delay constraints. • Minimize maximum delay • subject to area (power) constraints. • Minimize power consumption. • subject to delay constraints. • Maximize testability.

7. Optimizing a single variable is a “Single Objective Opt Problem” • Optimizing more than one objective is called “Multi Objective Opt” • In Multi Objective Opt there is no one Global Opt but a Pareto Optimal set of solutions.

8. Example: Area-Delay Trade-off

9. For complicated designs it is difficult to use only Two Level!! • A Fan in of a typical gate is usually 8 or less!!

10. Simple glue logic might use 2-level logic but real designs are a network of more than 10 levels of logic. • The circuit above can have between 3-8 logic gates per level • With Multi-Level Logic Synthesis we can control the number of levels we seek thus the speed of the circuit.

11. Two-Level (PLA) vs. Multi-Level E.g. Standard Cell Layout PLA control logic constrained layout highly automatic technology independent multi-valued logic input, output, state encoding Very predictable Multi-level Logic all logic general (e.g. standard cell, regular blocks,..) automatic partially technology independent some ideas part of multi-level logic Very hard to predict

12. Optimization Criteria for Synthesis • The optimization criteria for multi-level logic is to minimizesome function of: • Area occupied by the logic gates and interconnect (approximated by literals = transistors in technology independent optimization) • Critical path delayof the longest path through the logic • Degree of testability of the circuit, measured in terms of the percentage of faults covered by a specified set of test vectors for an approximate fault model (e.g., single or multiple stuck-at faults) • Power consumed by the logic gates • Noise immunity • Placeability, Wireability • Manufacturability • while simultaneously satisfying upper or lower bound constraints placed on these physical quantities

13. Multilevel Logic Synthesis Problem • Goal: • Model the multilevel logic • Optimize the logic based on the cost criteria • Difficulty: • Multilevel gives more design freedom and increases the design complexity • Technology dependent/independent views • Models: • Algebraic forms • Boolean networks • Optimization Techniques: • Exact method: few, exponential complexity, impractical • Approximation method: heuristic algorithm, rules-based methods

14. Network Representation In implementing multi-level logic our first aim is to establish a structure on which to develop a theory and algorithms • independent of technology on which manipulations can be made, and • optimization progress can be well estimated. This leads to two abstractions: • Boolean network • Factored forms

15. Circuit Modeling • Boolean Logic network • Interconnection of logic functions. • Hybrid structural/behavioral model. • Bound (mapped) networks • Interconnection of logic gates. • Structural model. Example of Bound Network

16. Boolean Logic Networks help, without viewing specific gates such as ordinary gate logic. • Unlike traditional Boolean logic circuit, the Boolean Network will allow us to model any complicated sub-circuit.

17. Example of a Logic Network

18. 9 • We will optimize the count of the literals! • What are the literals? The sum of all variables in the bubbles. • Y represents an internal output of the first bubble. • How will we be able to Optimize the Multilevel Logic Network?

19. Estimation • Area • Number of literals • Corresponds to number of polysilicon strips (transistors) • Number of functions/gates. • Delay • Number of stages (unit delay per stage). • Refined gate delay models (relating delay to function complexity and fanout). • Sensitizable paths (detection of false paths). • Wiring delays estimated using statistical models.

20. Problem Analysis • Multiple-level optimization is hard. • Exact methods • Exponential complexity. • Impractical. • Approximate methods • Heuristic algorithms. • Rule-based methods. • Strategies for optimization • Improve circuit step by step based on circuit transformations. • Preserve network behavior. • Methods differ in • Types of transformations. • Selection and orderof transformations.

21. Thus Two Level Logic Synthesis will help in Multi Level Logic • Simplify, Remove, Add (3 Operators that need to be applied). • Factoring is the heart and soul of Multilevel Synthesis!!

22. Simplifying a node can be performed by a tool such as ESPRESSO (optimize 2-level logic) • Removing a node entitles pushing the Operation along with the variable to the next nodes (Making them bigger!) • We can then simplify the new bigger nodes with 2-level techniques.

23. Adding new nodes (Factoring) is the interesting and hard part of Multi-Level Logic Optimization. • The effect of factoring leads to expressions with less literals. • However the design on the right has more delays (no free lunch!) • Thus we are exploring the solution and design space!!

24. Transformations for Logic Networks • Heuristic methods for multiple-level logic optimization perform a stepwise improvement of the network by means of ``Logic Transformation” that preserve the input/output network behavior. • Examples of Transformations: • Elimination • Decomposition • Extraction • Simplification • Substitution

25. Elimination • Eliminate one function from the network. • Perform variable substitution. • Example • s = r +b’; r = p+a’ •  s = p+a’+b’. • Thus the number of levels (stages) decreased!

26. Decomposition • Break one function into smaller ones. • Introducenew vertices in the network. • Example • v = a’d+bd+c’d+ae’. •  j = a’+b+c’; v = jd+ae’

27. Extraction or Factoring … • Find a common sub-expression of two (or more) expressions. • Extract sub-expression as new function. • Introduce new vertex in the network. • Example • p = ce+de; t = ac+ad+bc+bd+e; (13 literals) • p = (c+d)e; t = (c+d)(a+b)+e; (Factoring: 8 literals) •  k = c+d; p = ke; t = ka+ kb +e; (Extraction: 9 literals)

28. … Extraction • p = ce+de; t = ac+ad+bc+bd+e; (13 literals) • k = c+d; p = ke; t = ka+ kb +e; (Extraction: 9 literals)

29. Simplification • Simplify a local function (using Espresso). • Example • u = q’c+qc’ +qc; •  u = q +c;

30. Substitution • Simplify a local function by using an additional input that was not previously in its support set. • Example • t = ka+kb+e. •  t = kq +e; because q = a+b.

31. Example: Sequence of Transformations Original Network (33 lit.) Transformed Network (20 lit.)

32. Optimization Approaches • Algorithmic approach • Define an algorithm for each transformation type. • Algorithm is an operator on the network. • Each operator has well-defined properties • Heuristic methods still used. • Weak optimality properties. • Sequence of operators • Defined by scripts. • Based on experience. • Rule-based approach (IBM Logic Synthesis System) • Rule-data base • Set of pattern pairs. • Pattern replacement driven by rules.

33. Heuristics do not guarantee an optimal solution. • The complexity of the heuristics is important!! • Multi Level Synthesis is more of an Art! • HOW DO WE DO FACTORING IN MULTILEVEL SYNTHESIS??

34. MLS: Algebraic Model • What is the Algebraic Model? • Advantages • Disadvantages • What is Algebraic Division? • Elegant Heuristic with constraints.

35. Algebraic Division (“Weak Division”)! • So what is the idea behind “Algebraic Model”?

36. Useful and very interesting … • Ignore all the identities in RED. • What are we going to gain? • What are we going to lose?

37. Losing expressive power reduces our chances of minimizing expressions! • However, we see only a list of products that can lead to ‘0’ or ‘1’

38. The heart of the Algebraic Model is to perform the following operation: (abc + bcd)/bc a + d • This would be powerful! • In the example on the LHS the divisor is called a factor if remainder=0

47. The Question is “How do we actually do this?”

48. MLS: Algebraic Division • Objectives of the Algebraic Model. • Pull out useful factors • How Algebraic Division works? • Elegant Heuristic with constraints.