UTB SOI for LER/RDF

1. UTB SOI for LER/RDF EECS Min Hee Cho

2. Introduction LER (Line Edge Roughness) RDF (Random Dopant Fluctuation) Variation Solution – UTB SOI Results Process of UTB Conclusion Outline

3. Introduction 1m size ball 3nm TR (1947) Price : less than 1 Nano dollar for each TR  cheaper and smaller However, So many problems occur! Process, SCE / fundamental problems LER, RDF etc

4. What is LER (Line Edge Roughness) As device shrinks, the roughness of gate edge become problem Actually surface is very rough. The contribution of gate edge roughness to leakage current and variability has been significantly increased with the MOSFETs scaling.

5. Variation due to LER Distribution plot frequency 200nm The main source of LER : *Polygrain structure at the interface *Thermal annealing process (such as poly reoxidation) * Litho-process 35nm channel length Rms=2nm Correlation length = 20nm Fundamental problem

6. What is RDF (Random Dopant Fluctuation) Boron implantation and distribution (MC simulation) * In short channel device  the number of dopants in channel can be different from device to device affects Vth characteristics *Long channel assumption : Doping distribution =continuous * Dopant is particle * Implantation or Diffusion :Each dopant distribute randomly. And we can’t predict its exact place.

7. Lg vs Current variation Variation of On-current vs Lg (Bulk Transistor) As Lg decrease, the RDF problem become severer

8. For example SNM- SRAM 200 cases 35nm Lg Vout Vin Many curves overlap It is very hard to get good properties of SRAM Size of square : Static noise margin  the larger, the better SNM become worse RDF – SNM in SRAM SNM of SRAM SRAM : composed of 6 Transistor Distribution plot for SNM

9. There are several solution for distribution  change the process (litho, implantation etc)  change the structure (Fin-FET, SOI etc.) In this review, I focus on UTB SOI (Ultra Thin Body Silicon on Insulator) Solution – UTB SOI

10. UTB SOI Raised S/D  reduced Resistance at S/D FD SOI (Thin Body)  Undoped Si  reduce RDF effect Gate LDD No S/D Junction leakage SOI (Si) Intrinsic BOX (SiO2) Thin SOI (5~10nm)  Fullly Depleted (channel region controlled by only gate tightly)  reduce lateral Field (Drain electric field)  reduce the Short Channel effect (DIBL) SCE is minimized  Even though Gate length reduced, Vt changes very little (Gate length dependece reduced)  LER effect reduced

11. Results Distribution plot for Vt LER only RDF only Distribution improved drastically

12. SRAM - SNM

13. Wet etch SOI(Thick Si) 2nm single crystal Si SOI(Si) BOX (SiO2) BOX (SiO2) Substrate (Si) Substrate (Si) Good controllability compared to CMP etc. We can use this tech. in FinFET : Thick Fin  oxidation  thin Fin structure Process of UTB Oxidation SOI(Si) 2nm Thin Body

14. As transistor shrinks, the fundamental problems such as (RDF, LER) become problems UTB SOI can be one of solutions UTB SOI : reduce lateral field  SCE↓ LER ↓ : FD  undoped Si  RDF ↓ Review process of UTB SOI Conclusion

15. “Simulation of Statistical Variability in Nano MOSFETs” Asen Asenov, 2007 VLSI “High Immunity to Threshold Voltage Variability in Undoped Ultra-Thin FDSOI MOSFETs and its Physical Understanding” O. Weber et al, 2008 IEDM “Evaluation of Intrinsic Parameter Fluctuations on 45, 32 and 22nm Technology Node LP N-MOSFETs” B Cheng et al, Solid-State Device Research Conference, 2008 “Intrinsic Parameter Fluctuations in Decananometer MOSFETs Introduced by Gate Line Edge Roughness” Asen Asenov et al., TED 2003 “Impact of SOI Thickness Fluctuation on Threshold Voltage Variation in Ultra-Thin Body SOI MOSFETs” Gen Tsutsui et al, TRANSACTIONS ON NANOTECHNOLOGY 2005 References

16. Q&A Thank you very much See you again!