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MISTRAL & ASTRAL Sensors Readout & Testability From FSBB 0 (Full Scale Building Bloc) toward FSP (Full Scale Prototype) Christine Hu-Guo - Gilles CLAUS (on behalf of PICSEL and ALICE teams of IPHC-Strasbourg). 9,2 mm. 16,9 mm. FSBB 0. 13,7 mm. 30 mm. FSBB. FSBB. FSBB. 12-13 mm. 15 mm.

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  1. MISTRAL & ASTRAL SensorsReadout & TestabilityFrom FSBB 0 (Full Scale Building Bloc) toward FSP (Full Scale Prototype) Christine Hu-Guo - Gilles CLAUS (on behalf of PICSEL and ALICE teams of IPHC-Strasbourg)

  2. 9,2 mm 16,9 mm FSBB 0 13,7 mm 30 mm FSBB FSBB FSBB 12-13 mm 15 mm Outline • FSBB 0 (Full Scale Building Bloc Version 0) • Main characteristics • Testability • Readout • FSP (Full Scale Prototype) : MISTRAL & ASTRAL • Main characteristics • Testability • Readout FSBB (Full Scale Building Bloc) EUDET Beam Telescope FSP (Full Scale Prototype) IPHC gilles.claus@iphc.cnrs.fr

  3. MISTRAL – ASTRAL : Simplified Bloc Diagram • MISTRAL • Pixel + Amplifier + CDS (Correlqted Double Sampling) • Analogic  Digital conversion  Discriminators • One discriminator at end of each column • Data compression logic  SUZE 02 • Data transmission  Serialiser • ASTRAL • Improvement of Upstream part • One discriminator per pixel • Same downstream part IPHC gilles.claus@iphc.cnrs.fr

  4. 9,2 mm 16,9 mm FSBB 0 13,7 mm 30 mm FSBB FSBB FSBB 12-13 mm 15 mm From FSBB toward FSP • FSBB 0 (Full Scale Building Bloc Version 0) • Two versions : FSBB MISTRAL & FSBB ASTRAL • Matrix 9,2 x 13,7 mm² - 416 x 416 pixels – Pixels 22 x 33 µm² • CMOS-Opto 0,18 µm process Tower Jazz • 3 x FSBB Submitted in February 2014 • FSP (Full Scale Prototype) : MISTRAL & ASTRAL • Based on a building block : FSP = 3 x FSBB • Matrix : 30 x 12-13 µm² ~ 1248 columns x 416 rows • MISTRAL : • Matrix 30 x ~ 13 mm² - 22 x 33 µm² • One discriminator per column • T r.o ~ 35 µs - P ~ 200 mW/cm² • ASTRAL • Matrix 30 x ~ 12 mm² - 24 x 31 µm² • One discriminator per pixel • T r.o <= 20 µs - P ~ 85 mW/cm² • Submission plans for end of 2014 FSBB (Full Scale Building Bloc) EUDET Beam Telescope FSP (Full Scale Prototype) IPHC gilles.claus@iphc.cnrs.fr

  5. FSBB 0 : Full Scale Building Block (Version 0) EUDET Beam Telescope IPHC gilles.claus@iphc.cnrs.fr

  6. 9,2 mm 13,7 mm 16,9 mm Mistral B Mistral A Astral 27,6 mm Full Scale Building Block (FSBB 0): MISTRAL & ASTRAL • Two versions : MISTRAL & ASTRAL • Three FSBB 0 submitted in One single chip • Chip ~ Equivalent size as FSP (Full Scale Prototype) • Two MISTRAL (M0a, M0b) • One ASTRAL (A0) • MISTRAL T r.o 41,6 µs - ASTRAL T r.o 20,8 µs • Chip organisation  3 Sensors in one chip • Each sensor has its own steering & readout – Common power bus for MISTRAL A & B • 3 Matrix 9,2 x 13,7 mm² - 416 x 416 pixels – Pixels 22 x 33 µm² • Steering: • Reset + FSBB Configuration (operating mode, bias, … ) by JTAG slow control • Input clock @ 160 MHz • Start signal (to synchronize the readout of multiple FSBB) • Readout: • Normal operation mode (After zero suppression)  4 Wires link @ DDR 640 Mb/s • Test modes (Analogue & Digital) to characterize pixels, discriminators • Digital : 4 Wires protocol • Analogue : 16 Analogue outputs IPHC gilles.claus@iphc.cnrs.fr

  7. 9,2 mm Pixel Array 13,7 mm SUZE Test PADS Serial Output Readout Control JTAG TMS TDO TCK RST TDI CLK_D MK_D Start D0 D1 CK (160 MHz) JTAG (CMOS) Data out (LVDS) (LVDS) Full Scale Building Block (FSBB 0): MISTRAL & ASTRAL • Steering & readout signals • Steering 5 CMOS + 2 LVDS • JTAG  5 CMOS lines • RST, TMS, TCK : Common all sensors • TDI, TDO : Daisy chained • Clock in (160 MHz)  1 LVDS • Start in  1 LVDS • Readout (640 Mb/s)  4 LVDS • MK_D (Synchro)  1 LVDS • CLK_D (160 MHz)  1 LVDS • Data D0, D1 DDR 320 Mb/s  2 LVDS • Testability  Test points : 11 Analogues + 2 Digital CMOS • MISTRAL • 4 VRef discri + 3 VTests discri • 4 bias • 2 digital (CMOS)  Spy internal signals • ASTRAL • 3 VRef discri • 2 Bias • 2 digital (CMOS)  Spy internal signals IPHC gilles.claus@iphc.cnrs.fr

  8. Full Scale Building Block (FSBB 0): MISTRAL & ASTRAL • Testabilityimplemented on FSBB : • Sensors configuration and status JTAG slow control (5 wires link) • Digital pads interconnection testing  JTAG boundary scan • Pixel characterization at analogue level  Analogue outputs of 8 columns  Fe55, Calibration peak, CCE, Noise • All discriminators characterization  Discri input = On-chip analogue signal  Scurve : Noise, Pedestal • All Pixel + discriminators characterization  Scurve : Noise, Pedestal + Fake hits rate • Data transmission & SUZE02 logic test  Pixels patterns emulation by JTAG • Sensor temperature  Read as analogue (2 pads) • Spy internal digital & analogue signals  2 LVDS test pads + n Analogues test pads EUDET Beam Telescope IPHC gilles.claus@iphc.cnrs.fr

  9. FSBB 0 Normal Readout & Data stream • Readout configuration: • Double Data Rate (DDR) @ 160 MHz  320 Mbit/s • Two options • Full memory : Two data link DDR @ 160 MHz  640 Mbit/s • Half memory : One data link DDR @ 160 MHz  320 Mbit/s • Data stream organization • Data generated on both edges (DDR) of FSBB output clock • Synchronization signal MKD • Data LSB first • Data stream is organized in 30 bits words multiplexed over the two links • First bit of frame = LSB of Header (30 bits) Two links @ 320 Mbit/s One link @ 320 Mbit/s IPHC gilles.claus@iphc.cnrs.fr

  10. FSBB 0 Data stream : Service & Data fields • Data words: 30 bits  W30 (30 bits words) • Mono output: • Dual output: • Data generated on both edges (DDR) of FSBB output clock @ 160 MHz (Bit time slot = 3,125 ns) • Service fields  Total 4 W30 / output • Header  1 W30 / output (Header 0 + Header 1) • Trigger  1 W30 / output • Frame counter, data length  1 W30 / output • Trailer  1 W30 / output (Trailer 0 + Trailer 1) • Data fields ( format on next slide ) • MISTRAL  Maximum = 416 x W30 / output • ASTRAL  Maximum = 208 x W30 / output • Total data stream size per output • MISTRAL  Max 13 312 bits / Output / 41,6 µs  Total (2 outputs) 76 MB/s • ASTRAL  Max 6 656 bits / Output / 20,8 µs  Total (2 outputs) 76 MB/s IPHC gilles.claus@iphc.cnrs.fr

  11. G1 G0 416 224 223 0 … … Delta (2bits) 3 State 0 Super Line X 2 State 0 1 State 1 0 State 1 3 Super Line X-1 2 1 0 FSBB 0 Data stream : Data fields format • The useful data is the daisy chain of "status" and "hit-windows" • Status:  "FSBB user manual" for details • One status field per super line • Indicates row address + the number of Hit-Windows • Hit-windows:  "FSBB user manual" for details • Up to 9 hit-windows / ½ line • Indicates : column address + Hit map + Window offset in super Line IPHC gilles.claus@iphc.cnrs.fr

  12. Full Scale Prototype : MISTRAL & ASTRAL EUDET Beam Telescope IPHC gilles.claus@iphc.cnrs.fr

  13. 30 mm FSBB FSBB FSBB 12-13 mm 15 mm Full Scale Prototype : MISTRAL & ASTRAL • Sensor organisation: • Composed of 3 x FSBB (Full Scale Building Block • Two versions • MISTAL = Mature architecture (STAR) • End of column discriminator • T r.o ~ 35 µs, Power ~ 200 mW/cm² • ASTRAL = Innovative architecture • In-pixel discriminator • T r.o<20 µs, Power ~ 85 mW/cm² • Steering: • Reset + FSBB Configuration (operating mode, bias, … ) by JTAG slow control • Input clock 160 MHz or 40 MHz with on-chip PLL implemented • Start signal (to synchronize the readout of multiple FSBB) • Readout: • Normal operation mode (After zero suppression)  One wire link 8B/10B @ 2 Gb/s • Test modes (Analogue & Digital) to characterize pixels, discriminators • Digital : One wire link • Analogue  To be define IPHC gilles.claus@iphc.cnrs.fr

  14. 30 mm Pixel Array Pixel Array Pixel Array 13 mm SUZE SUZE SUZE JTAG Test PADS Serial Output Readout Controller PLL TDO TMS TCK RST TDI Data out (LVDS) Start CK (40 MHz) CK (160 MHz) Only one output 8B/10B Protocol @ ~ 2 Gb/s JTAG (CMOS) (LVDS) (LVDS) Input clock 40 MHz Via on-chip PLL Full Scale Prototype : MISTRAL & ASTRAL • Steering & readout signals • Steering  5 CMOS + 2 LVDS / Ladder • JTAG  5 CMOS lines / ladder • RST, TMS, TCK : Common all sensors • TDI, TDO : Daisy chained • Clock in  1 LVDS / ladder • Start in  1 LVDS / ladder (Optional ? ) • Readout  1 LVDS / Sensor • Data out 8B/10B  1 LVDS / sensor • Clock embeded in data stream • Testability  0 Pads / Ladder • No pads required on the ladder • Pads required for probe testing  Nb ? • 2 LVDS outputs  4 pads • N Analogue outputs  N pads • 1 Input to characterization ADC  1 pad • n Analogue internal references  n IPHC gilles.claus@iphc.cnrs.fr

  15. 30 mm 30 mm Pixel Array FSBB M0a Pixel Array FSBB M0b Pixel Array FSBB A0 Pixel Array FSBB Pixel Array FSBB Pixel Array FSBB 13 mm 13 mm SUZE SUZE SUZE SUZE SUZE SUZE MEMORY MEMORY MEMORY MEMORY MEMORY MEMORY 3 x // Bus 120 bits @ 5,5 MHz 3 x // Bus 120 bits @ 5,5 MHz SERIALISER SERIALISER SERIALISER MEMORY BUFFER ? + MANAGMENT Single output Clock emdeded in data stream 8B/10B Protocol SERIALISER 8B/10B Encoding (INFN Torino) MK_D MK_D CLK_D CLK_D MK_D CLK_D D0 D1 D0 D1 D0 D1 Data out FSBB M0 A 640 Mb/s / Data out FSBB M0 B 640 Mb/s Data out FSBB A0 640 Mb/s Worst case  Data out 3 x 640 Mb/s ~ 1,9 Gb/s Full Scale Prototype : Serial output 8B/10B • FSBB • One link / sensor • 4 LVDS pairs / link • FSS • Three sensors mutiplexed on one link • 1 LVDS pairs / link (8B/10B protocol) Safety factor of ~ 2 Can reduce output data rate 2 Gb/s  1 Gb/s IPHC gilles.claus@iphc.cnrs.fr

  16. Full Scale Prototype : MISTRAL & ASTRAL • Testability  Green = OK / Orange = To Do / Wish list • Sensors configuration and status JTAG slow control (5 wires link) • Digital pads interconnection testing JTAG boundary scan • Pixel characterization at analogue level  Fe55, Calibration peak, CCE, Noise • Easy to implement on MISTRAL • Study needed on ASTRAL • All discriminators characterization  S curves : Noise, Pedestal • All Pixels + discriminators characterization  Scurve : Noise, Pedestal + Fake hits rate • Data transmission & SUZE02 logic test  Hard coded pixels patterns emulation • Sensor temperature  Read as analogue (2 pads) & By JTAG • Power supply measurement & bias  Internal ADC read by JTAG • Spy internal digital & analogue signals 2 LVDS test pads + n Analogues test pads EUDET Beam Telescope IPHC gilles.claus@iphc.cnrs.fr

  17. Summary • FSBB 0 • Submitted in February 2014 • Detailed documentation for ~ 1 April 2014  FSBB User manual • Should be back from foundry ~ end of May 2014 • Next steps • First Tests & Characterization results (at laboratory) expected for end of June • Define testability to be implemented in Final Sensor Prototype (FSP) • FSBB 0 beam test in October 2014 (Using FSBB Telescope) • FSP submission at the end of 2014 IPHC gilles.claus@iphc.cnrs.fr

  18. Backup IPHC gilles.claus@iphc.cnrs.fr

  19. Full Scale Sensors (FSS): JTAG Slow control Slow Control ( JTAG ) – Mimosa 26 configuration • TCK frequency • Using PC // port  Few 100 Khz • Mimosa / FSBB limits  10 – 20 MHz • Run on STAR Experiment @ 1,5 MHz JTAG via PC // Port IPHC gilles.claus@iphc.cnrs.fr

  20. IPHC gilles.claus@iphc.cnrs.fr

  21. IPHC gilles.claus@iphc.cnrs.fr

  22. IPHC gilles.claus@iphc.cnrs.fr

  23. IPHC gilles.claus@iphc.cnrs.fr

  24. IPHC gilles.claus@iphc.cnrs.fr

  25. IPHC gilles.claus@iphc.cnrs.fr

  26. IPHC gilles.claus@iphc.cnrs.fr

  27. IPHC gilles.claus@iphc.cnrs.fr

  28. IPHC gilles.claus@iphc.cnrs.fr

  29. IPHC gilles.claus@iphc.cnrs.fr

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