한양대학교 과학기술학부 응용물리학전공 강 보 수

1. 03.17.2010 Metal-oxide thin film applications for storage device 한양대학교 과학기술학부 응용물리학전공 강 보 수

2. Outline RRAM Review of next-generation nonvolatile memory candidates Resistance switching in nanometer scale Oxide Diode switch element to embody RRAM array Reduction of reset current Summary

3. 컴퓨터 사양의 체감상 변화

4. 비휘발성 메모리 소자 2010/2/10 • Continuous scaling requires advances in • Fabrication techniques • Device design • Material growth…

5. Universal Memory: next generation memory? Further scaling is approaching physical and technological limits. - leakage current via direct tunneling - extremely high cost for lithography Non volatile, high density, high speed reading and programming memories are desired for next generation memory. Breaking the Scaling Barrier  New opportunity for new memory structures and new materials

6. Bistable physical states and nonvolatile memory MRAM ( Magnetic RAM ) PRAM ( Phase-Change RAM ) FeRAM ( Ferroelectric RAM ) Polarization up or down Spin parallel or antiparallel Amorphous or crystalline Different current flow when P flips Different resistance Different resistance

8. ITRS for Emerging Research Devices 2004 ITRS (Emerging Research Devices) 2007 ITRS (Emerging Research Devices) • Emerging Research Devices of ITRS • In 2004, insulator resistance change memory included • In 2007, 1D1R device included

9. Resistance switching Memory switching with two (or more) stable states Unipolar resistance switching Bipolar resistance switching reset set Threshold switching mono-stable

10. - anode + + + + + + + + + - - + - + + + + + + + + + + - - - Various resistance (memory) switching mechanisms Thermal a.k.a. Fuse/Antifuse type Electronic High R (V = 0) Forward (V < 0) Low R (V = 0) Reverse (V > 0) Ionic a.k.a. Programmable Metallization Cell

11. RESET SET Forming Reset Forming Set Unipolar resistance switching mechanism Forming process: creation of filamentary conduction paths (local reduction of oxide) Reset process: rupture of filaments (thermal + re-oxidation) Set process: reconnection of the disconnected paths Simulated with random circuit breaker (RCB) network model S.C.Chae et al. Adv. Mater. (2008).

12. Unipolar resistance switching simulated by RCB model

13. RRAM Review of next-generation nonvolatile memory candidates Resistance switching in nanometer scale Oxide Diode switch element to embody RRAM array Reduction of reset current Summary

14. Best for Memory Switching Metallic 0 10 20%, 10um, 1000A -1 10 -2 10 -3 10 Current (A) -4 10 -5 10 -6 10 -7 10 -8 10 -3 -2 -1 0 1 2 3 Voltage Electrical properties of NiO thinfilms depending on oxygen content Bistable Memory Switching Monostable Threshold Switching S. Seo et.al., APL 85, 5655 (2004)

15. Sample preparation (Metal-Insulator-Metal structure) L Si substrate Pt deposition (50 nm thick) NiO deposition (30 nm thick) Pt deposition (50 nm thick) L=10 um ~100 um: photo-lithography L=100 nm ~ 1 um: e-beam lithography L~10 nm : metal-coated probe tip for Atomic Force Microscopy - Measurement equipment +

16. Electrical measurement of Pt/NiO/Pt thin film Adv. Mater. 20, 924 (2008). • Black: Monitoring-writing-monitoring pulse train • Blue: output voltage*output impedance at oscilloscope • When the cell is in LRS, most of the voltage is applied to the oscilloscope. • When the cell is in HRS, most of the voltage is applied to the cell.

17. Scalability of switching current, power, time Nano Letters 9, 1476 (2009). Switching energy=power*time Energy density=energy/area Switching power=Vreset*Ireset • Reset current, power, time decrease as cell area is reduced. • Resistance switching occurs in a way that energy density is preserved.

18. Reset by oxidation of filaments Extrapolation to molecular dimension (0.5x0.5 nm2) gives the switching energy of tens of electron volts. ~ migration energy of oxygen atoms

19. What can happen to filaments as cell area is reduced The resistance of the LRS increases as the area is reduced, which implies… The number decreases. The total X-sectional area of the filaments decreases. Thinner filaments are formed. or The R of the individual filament increases. Less conductive filaments are formed.

20. RRAM Review of next-generation nonvolatile memory candidates Resistance switching in nanometer scale Oxide Diode switch element to embody RRAM array Reduction of reset current Summary

21. Methods to increase memory density per area • Muliti-chip packaging • Multi-Level Cell • Multi-Layer Stacking

22. Resistance memory device in 4F2 design and beyond Resistive memory: an electrically switchable two-terminal memory cell Cross-point array: stackable structure with shared access lines Rectifying element: preventing unintended misreading detour 1D 1R Cross-point memory

23.  to provide the maximum current needed in cell operation  to reduce leakage currents and enable a large block of array switching current of the storage node current density of the switch element determine the limitation of scalability ~30 nm Requirements of the diode • High forward current density • High On/Off current ratio • Low process temperature • to realize 3D stackable memory (High temperature Si diode is not available.)

24. Different nature of Pt/IZO contacts • Pt and InZnOx were both RF-sputtered at room temperature. 10 m J = Jo [exp(qV/nkT)-1] n-IZO Pt SiO2/Si Pt Tunneling contact EC EF n-IZO Pt TE Pt BE Top surface can be oxygen-deficient.  Tunneling contact? High oxygen vacancy concentration

25. Aging effect on the Pt/IZO/Pt Schottky diode The aged diodes can no longer be clearly described by J = Jo [exp(qV/nkT)-1]. Reverse current of the aged diodes greatly increased. Significant tunneling current through the bottom Schottky barrier is suspected.

26. Depletion-layer capacitance, C C=єs/W (1/C)2=2(Vbi+V)/(qєsNd) W=[2єs(Vbi+V)/(qNd) ]1/2 Capacitance-Voltage measurement with AC metal n metal n - - - + + + - - - ++ ++ ++ More reverse bias - - - Reverse bias freq: 1MHz, amp: 100mV

27. C-V measurement with AC: Enhanced tunneling current Pristine Aged n n M M High built-in bias, High concentration, Thin depletion width  more tunneling current

28. Photoluminescence Appl. Phys. Lett. 92, 233507 (2008). Near band-edge emission Blue-green emission Vo or Zni in ZnO Vo in In2O3 • More defects in aged sample • Enhances tunneling if present near the space charge region • The identified defects are responsible for • Increasing the electron concentration, and • Forming tunneling paths in the Schottky barrier

29. CuO and InZnOx, our choice for heterojunction Electron contribution’s dominant 1eV ~1.3 eV ND=1018 Wp xp 10 ~3.4 eV NA=1018 Wn CuO with small bandgap InZnOx with low resistivity xn Wn Negligible hole contribution

30. Rutherford Backscattering Spectroscopy InZnOx: RF sputtering with InZnOx target at room temperature CuO: DC reactive sputtering with Cu target at room temperature InZnOx/SiO2/Si In:Zn=1.0:1.0 CuO/SiO2/Si Cu:O=49.4:50.6 Copper vacancy is known as the origin of p-type conduction of CuO.

31. Effects of thickness and growth condition Too small thickness or low oxygen content cause the increase of reverse current.

32. Diode ideality factor n epi-Si diode : 1~2 many oxide diodes : 2~5 Current density – Voltage curve Adv. Mater. 20, 3066 (2008). Half-wave rectification n~2 Delay < ~10 ns (Fast transient behavior) • Max. forward current density~3.5x104 A/cm2 • (the highest value for oxide diode currently found in literature) • On/Off current ratio~106 • Turn-on threshold voltage~0.7 V and 1.2 V

33. Current status of Oxide diodes Selective-Epitaxial-Growth Si diode Poly-Si diode a-Si diode

34. 2nd Stack NiO Diode 1st Stack Diode 100 nm NiO 1st Stack 2nd Stack Read @1V Read @1V • No Interference between the layers • Read window margin > 102 The First 1D1R stackable memory array 8x8 Array 1st layer 2nd layer

35. Pt NiO Pt Pt CuO/InZnO Pt Pt NiO Device components for stack architecture NiO Memory element 1D1R cell ZnO TFT • High current driving • Low temperature process < 300 °C  Suitable for stackable memory [IEDM (2008) ]

36. IV Characteristics of 1D1R Memory Cell 1D1R cells with GIZO TFTs Schematic diagram • Operation of 1D-1R cell with select transistor biased to off, and on in both saturation and in linear regime. Adv. Funct. Mater. (2008)

37. Outline RRAM Review of next-generation nonvolatile memory candidates Resistance switching in nanometer scale Oxide Diode switch element to embody RRAM array Reduction of reset current Summary

38. 100 nm High reset current problem in RRAM Present status of RRAM Final goal of reset current • Two important problems • Reducing reset current • low power consumption and reliable operation 1D-1R or 1T-1R devices structure

39. 1th 2th 3th 4th Understanding of conducting filament generation in oxide Forming process In Unipolar resistance switching, Conducting filament generation decides reset current.  How can we block excessive conducting filament generation?

40. Pt/FeOx/Pt S. B. Lee, JKPS 51, S96 (2007) Compliance current Pt/NiO/Pt Pt/TiO2/Pt C. Rohde, APL 85, 262907 (2005) S. Seo, APL 85, 5655 (2004) Control parameters of reset current Pt/Ti:NiO/Pt S.-E. Ahn, Adv. Mater. 20, 924 (2008) !! Compliance current !!  We restrict current level to avoid electric breakdown during forming & set processes.

41. ri rh V rl Dv VR VS Physical meaning of compliance current RCB network model Current compliance Random circuit breaker (RCB) network model 1 A 2 A Physics: Compliance current controls percolating growth of conducting filaments. Idea: How can we reduce compliance current to solve high reset current problem? 3 A

42. Unipolar resistance switching of Pt/SrTiO3-x/Pt Pt/SrTiO3-x/Pt capacitors SrTiO3 is very famous material for high-k applications. Therefore, many methods for reducing leakage current have been developed.

43. Reduction of leakage current of SrTiO3-x Nb Pure Al Acceptor doping : Co, Mn  decrease of current Donor doping : Nb  increase of current Mn Co doping pure 0.2 % Co 1.0 % Co S. Y. Wang, APL 84, 4116 (2004) and many references

44. Reduction of leakage current of SrTiO3-x Note: we made all materials in same PLD conditions. All acceptor doped SrTiO3-x show good unipolar RS. Leakage current Nb:STO > pure STO > Co:STO > Mn:STO

45. I-V curves of undoped/doped STO for various Icomp value

46. Pt/NiO/Pt NiO: I. G. Baek, IEEE 587 (2004) NiO (plug-BE): I. G. Baek, IEEE 750 (2005) Ti:NiO: S.-E. Ahn, Adv. Mater 19, 73 (2008) Reset current reduction using compliance current Small compliance current reduce reset current by 1/20. We can reduce compliance current using acceptor (Mn or Co) doping in SrTiO3-x. If we reduce electrode sizes, we can more reduce compliance current.  Reducing reset current. Note: we control “forming” & “set” processes with same compliance current.

47. Very important problem to reduce the reset current  Reset current IR is not scaled with Icomp. The relationship of IR≈ Icomp was maintained down to Icomp = 0.7 mA using external transistor.

48. Unipolar RS of acceptor doped SrTiO3-x Current levels near “forming” process We can reduce compliance current in Co and Mn.  Smaller than pure STO by the order of 1~2.

49. Summary • Pt/IZO/Pt Schottky diode showed an asymmetric J-V characteristics, possibly due to the tunneling contact at the top interface. Aging caused the increase of donor-like defects such as oxygen vacancies and zinc interstitials. Consequently, serious degradation in rectification property occurred. • A room-temperature-grown oxide thin film diode with the highest current density could be achieved by employing p-type CuO with small bandgap and n-type InZnOx with low resistivity. • Control of compliance current can be one of the ways to reduce the high reset current of unipolar resistance switching. • Difficulties in further (1) reduction of reset current in NiO, • (2) increase of current density of oxide diode, and • (3) lowering of process temperature of poly-Si diode • must be solved to realize 3D ReRAM array.

50. 감사합니다.