The Module Controller Chip (MCC) of the ATLAS Pixel Detector

1. The Module Controller Chip (MCC) of the ATLAS Pixel Detector ATLAS Pixel Detector Collaboration Albany, Berkeley, Bonn, Dortmund, Irvine, Genova, Marseille, Milano, New Mexico Nikhef, Oklahoma, Prague, Santa Cruz, Siegen, Udine, Wisconsin, Wuppertal Presented by: G. Darbo / INFN - Genova e-mail: darbo@genova.infn.it • Introduction: the Pixel Module; • MCC Architecture; • Prototype Chip Design; • Conclusions: Plans for the Future. • References: Talks at this workshop by: G. Gagliardi - System Requirements K.Einsweiler & T.Kuhl - Front-End Chips Documents: Atlas Pixel Demonstrator: System Architecture Which can be found at the URL: http://www.ge.infn.it/ATLAS/Electronics/home.html

2. The Detector Module ATLAS Pixel Module Layout (base line solution): • Front-End (FE) chips bump-bonded to the detector (16 / module); • Interconnection layer glued on detector back side; • MCC put on top. 2.228 tesseras (= modules) Chips = 16 FE + 1 Contr. (MCC) Channels = 61.440 Pixel Size = 50 x 300 m FLEX CIRCUIT MCC COOLING PIPE FRONT-END DETECTOR DETECTOR FLEX CIRCUIT WIRE BONDS

3. Module Architecture • Data Push architecture: FE hits transmitted as soon as ready; • Serial Data Links from FE’s to MCC • LVDS links using low current drivers (500 A); • 40 Mb/s transfer rate; • Point-to-point data link topology (Star Topology); • Fault tolerance; • High bandwidth  Low FE buffer occupancy, Smaller FE buffer size. MCC FE#0 DO DTI0 DCI DTI1 DI DTO XCK DTI15 CK LV1 GA0 SYNC DAO GA1 GA2 CCK GA3 LD XCK LV1 SYNC FE#1 DO CCK LD DI XCK LV1 GA0 SYNC GA1 GA2 CCK GA3 LD Legend FE#15 DO DI LVDS XCK LV1 GA0 SYNC GA1 CMOS GA2 CCK GA3 LD

4. MCC System Functions • System Configuration: • Individual FE addressing to R/W configuration data before run starts; • MCC initialization of the “Register Array” with run configuration; • R/O of status error register inside the MCC. • Event Building: • Event pushed by FE chips; • MCC collects the parallel data stream from all of the FE and stores them before starting event building; • MCC starts event building once it has completely received one event; • Event is formatted and transmitted out of the module; • Reports of Errors / Warning conditions in event building. • Timing, Trigger & Control: • Sends LV1 triggers to FE chips; • Keeps event synchronization in case of buffer overflows, and truncated / lost events; • Sends re-synchronization signals to recover from illegal conditions; • System Test: • Internal registers to monitor illegal conditions; • “Transparent Mode” to MCC bypass in accessing the FE chips; • I/O Signals: • Serial transmission to reduce interconnections and power; • LVDS type of signals for all the lines active in Run Mode.

5. MCC Architecture DTI 15 SYNC DTI 0 DAO XCK LV1 CCK LD FRONT END PORT RECEIVER RECEIVER CHANNEL RECEIVER 15 REGISTER TTC 0 CTRL BANK FIFO . 25 x 32 PEND. EV. CNT REC/TRAN EN EN 25 EVENT LV1-CNT BUILDER EOE DATA DATA EVENT'S COMMAND PENDING SCORE DECODER DATA LV1 FIFO BOARD CTRL TRANSMITTER MODULE PORT PORT XCKIN DTO DCI CK

6. . E o E E o E / W N G # 0 L V 1 # F r o m R E C E I V E R F E C T R L W N G # 1 W . P T R L D L . P T R L D F I F O R . P T R T o E v e n t B u i l d e r T o E v e n t B u i l d e r S c o r e B o a r d Architecture: Receiver Channel RECEIVER CHANNEL RECEIVER • Serial data from FE chips stored into a FIFO; • End-of-Event (EOE) detected upon arrival and sent to the Event Builder scoreboard; • 3 FIFO Pointers: • R.PTR: Read pointer controlled by the Event Builder; • W.PTR: Write poiter incremented at every new hit, loaded with L.PTR in case of FIFO overflow; • L.PTR: Last event pointer points to the end of last complete event. 0 CTRL FIFO 25 x 32 EN

7. . Architecture: Event Builder EVENT BUILDER LV1-CNT EOE • Event Builder (EVB) checks the scoreboard for a complete event; • EVB Extracts data for one event from each FIFO, it adds LV1# from the Pending LV1 FIFO and it sends the formatted event to the output of the module; • EVB handles error and warning conditions. EVENT'S PENDING SCORE LV1 FIFO BOARD CTRL TRANSMITTER Serial Data From Front-End Chips FIFO 15 FIFO 0 FIFO 1 FIFO 2 EVENT BUILDER OUT SERIAL TRANS. FIFO# 0 1 2 3 4 5 15 . 5 Event 4 LV1# 3 Ready 2 for 1 Building 0 E ' S B VENT S CORE OARD

8. Architecture: TTC TTC Trigger, Timing & Control (TTC) controls the signals: LV1 Level 1 Trigger SYNC-FE re-synchronize FE chips and front-end side of the MCC SYNC-MCC re-synchronize the whole MCC: LV1 counter is reset; • LV1: • Limit number of pending LV1: the number of pending LV1 can be limited between 1 and 15 (parameter in the register bank) • Contiguous LV1 (1  15) to FE chips can be generated upon a received LV1; • LV1 delayed to FE chips in units of clock cycles (25 ns) to adjust timing • SYNC-FE: • Automatic reset, to avoid out of sync events, is sent to FE chips each time no pending LV1 exist (this option can be disabled); • SYNC-FE can be executed sending a “Fast Command” to the MCC; • SYNC-MCC: • Similar to SYNC-FE to synchronize the MCC; • Executed by sending a “Fast Command” to the MCC.

9. Architecture: Command Decoder COMMAND DECODER • The command set is divided in 3 groups: Trigger: LV1 trigger command is 3-bit long  75 ns minimum LV1 spacing. Fast: 7-bit fixed length commands.  May be interleaved with trigger commands without taking the system out of run mode. Slow: Variable length commands (> 11 bits).  If issued in run mode, the MCC puts itself in configuration mode.  WrFrontEnd & RdFrontEnd activate the the protocol signals to configure the FE chip (DAO, LD, CCK).  Simulated events can be loaded by WrReceiver to exercise the Event Builder. • Command Set: Type Name Description Trigger LV1 LV1 Trigger Fast SyncFE Re-synchronize FE chips and MCC Fast SyncMCC Re-sync. FE chips, MCC & LV1 counter Fast PushEvent Push next event out Slow WrRegister Write to MCC register Slow RdRegister Read from MCC register Slow WrFifo Write a word to the enabled FIFO Slow RdFifo Read a word from the addressed FIFO Slow WrFrontEnd Write to the FE chips Slow RdFrontEnd Read (or R/W) from the Enabled FE chips Slow WrReceiver Read (or R/W) from the Enabled FE chips Slow EnDataTake Enable Data Take (put MCC in run mode) Slow SoftReset Software reset

10. Architecture: Register Bank REGISTER BANK • The MCC architecture allows for 16 general purpose registers: 11 are implemented in the current chip version; • All registers can be read/written and are up to 16-bit long; • The 11 registers are for: Control: GCR, LV1A, LV1B, FEEN Status: GSR Err./Wng.: ERR0, WNG0, WNG1 ILLC Protocol: CCNT, DCNT • The registers implemented are: Register Addr Description GCR 0 Global Control Register GSR 1 Global Status Register LV1A 2 LV1 Reg: 8-bits LV1 counter LV1B 3 LV1 Reg: No. of contig. LV1 & No. of pending LV1 & LV1 delay. FEEN 4 Front-end enable: 16-bit pattern to select active FE chips ERR0 5 Errors from front end FIFO: 1-bit flag from each of the 16 FIFO’s WNG0 6 Warning #0 from FE chips (truncated events, 1-bit flag) WNG1 7 Warning #1 from FE FIFO controller (truncated events, 1-bit flag) ILLC 8 Illegal command (copy of the issued command) CCNT 14 Length of control part in the message to the FE chips DCNT 15 Length of data part in the message to the FE chips

11. Architecture: Test Logic • MCC can be put into transparent mode to directly access FE chips: • All FF’s (~2000) are chained up for test: In  Out or Ring chain. LOGIC LOGIC LOGIC D D D Q Q Q CK CK CK CK CK TSTOUT Q SD SD SD TSTIN SD SE SE SE SE TSTEN<1:0>

12. R / O C T R L Signals: in Run Mode • In Run Mode operation all active signal are of LVDS type: CK / XCK / XCKIN - 40 MHz clock to MCC and to FE chips DCI - Data Command Input, Trigger and Slow commands LV1 - Decoded trigger pulse to FE chips SYNC - Re-synchronize signal to FE chips DTI - 16 lines Data Input from FE chips (500 , 500 µA) DTO - Data Output (module output, 3 mA) Front-End Chip Port DTI DTI DTI SYNC XCK LV1 C M D / T T C DTO XCKIN CK DCI Module Port .

13. Signals: in Configure Mode • In Configure Mode operation all active signal are LVDS / CMOS type. The CMOS signals are: RSI / RSO - Reset Input (to MCC) / Reset Output (to FE) CCK - Control Clock (5 MHz), used by FE chip to strobe data in or to produce data out. LD - Load signal to select Ctrl / Data sent to FE chips DAO - Data & Address information to the FE chips Front-End Chip Port DTI DTI DTI CCK DAO RSO LD . C M D / T T C R / O C T R L DTO XCKIN DCI RSI CK Module Port

14. H I T # n H I T # n + 1 H I T # n + 2 T I M E a ) H L V 1 # R O W # / W N G # C O L # 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 b ) H L V 1 # R O W # / W N G # C O L # T O T 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 4 1 3 1 2 1 1 8 7 6 1 0 0 5 0 1 0 0 1 5 0 n s t X C K D O  X C K F E - D O Protocol: FE Port • Single hit data transmission: Header - 1 bit to wake up receiver LV1 - 4-bits to check event trigger number Row# / Col# - Row (8-bits) / Column (5-bit) number ToT - 8-bit Time over Threshold information (optional) • Data are validate by positive clock (XCK) edge

15. 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 1 2 0 0 1 4 0 0 1 6 0 0 n s T I M E E x a m p l e 1 : L V 1 # - F E # - R O W # / C O L # - R O W # / C O L # - F E # - R O W # / C O L # E E n n c c o o d d i i n n g g L L e e g g e e n n d d : : Protocol: Module Port • Variable length event frame format: Header / Sync / Trailer - 8 / 13-bits records separated by Sync bit and terminated by a 13-bits trailer • Each event record starts with: trigger number (LV1 - 8-bits), followed by up to 16 FE chip number (FE# - 8-bits) each one follwed by a variable number of hit coordinates (ROW# / COL# - 13-bits). 0 E x a m p l e 2 : L V 1 # - F E # - R O W # / C O L # / T O T - R O W # / C O L # / T O T LV1# : 8-bits FE# : 8-bits ROW# : 8-bits / COL# : 5-bits / TOT : 8-bits Header or Sync : 1-bit Trailer = 0.0000.0000.0000 Trailer ToT = 0.0000.0000.0000.0000.0000

16. Design Methodology • Design Flow: Design Entry: • Behavioral Verilog Description Logic Synthesis: • Mapping to AMS standard cells using Synergy (Cadence) Routing: • Standard Cells + FIFO’s + I/O routed by Cell Ensemble (Cadence) DRC / LVS • Flat DRC and LVS Test Vectors • Design simulated using Behavioral and Gate Level Verilog description. Capacitance of 2 metal layer back- annotated into Verilog simulation to perform timing check. • ~ 700.000 test vectors generated to test MCC at silicon foundry. Verilog Synthetized Schematics Routed

17. The MCC Prototype Module Cells Gatecount Command Decoder 1613 3809.0 Event Builder 3145 9177.0 Receiver Chan (ex. FIFO) 701 2887.0 Register Bank 1405 2954.0 TTC 273 669.0 MCC Total 17922 63874.0 Chip Size: 10.6 x 6.3 = 66.8 mm2 No. of Trans.: layout = 416.464 schematics = 363.016 No. of Pins: 83

18. MCC Status & Future Plans • MCC version 1.0 submitted to AMS: end of April ‘98. • CMOS 0.8 µm, 2 metal, 2 poly process; • 15 4”-wafers processed in 7÷8 weeks; • MCC samples tested at foundry site. • MCC large digital design: • 16 full custom FIFO’s with 2 ring pointers and a shadow pointer register. 32 words x 25 bits; • Special designed LVDS drivers/receivers • ~18.000 standard cells implementing the full functionality. • Future Plans: • Test the prototypes: next summer; • Architecture changes: direct optical driver / receiver interface; • Move to rad-hard  DMILL: start today, chips spring ‘99. Acknowledgments: To MCC co-designers R. Beccherle, G.Comes, G.Gagliardi, G.Meddeler & P.Musico