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IDE Controller

IDE Controller. Group Members Brian Kulig Graig Plumb James Pierpont Saif Shaikh Advisor Arun Ramanathan. Development of an Ultra DMA Module for a Hard Disk Controller. Specifications – IDE ATA5 Standards

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IDE Controller

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  1. IDE Controller Group Members Brian Kulig Graig Plumb James Pierpont Saif Shaikh Advisor Arun Ramanathan

  2. Development of an Ultra DMA Module for a Hard Disk Controller • Specifications – IDE ATA5 Standards • RTL Description of PIO and Ultra DMA (Direct Memory Access) Module in Verilog HDL (Support for PIO Modes 0 to 4 & UltraDMA Modes 0 to 4) • Behavioral description of the Hard Disk Interface • Functional and Timing Simulations using Cadence VerilogXL

  3. Architecture IDE CHANNEL0 IDE FSM PIO MODULE To Hard Disk Fifo’s and Rest of System DMA MODULE PIO MODULE IDE FSM To Hard Disk Fifo’s and Rest of System DMA MODULE IDE CHANNEL1

  4. Ultra DMA • Modes 0-4 • Data In(Out) • Initiate Data-in(out) Burst • Transfer the Data • Pause Data-in(out) Burst • Terminate Data-in(out) Burst

  5. Ultra DMA Constraints

  6. Programmed I/O • Modes 0-4 • Replicate Timing Diagrams Presented In ATA/ATAPI - 5 Standards • Much Simpler Than Ultra DMA

  7. Programmed I/O Constraints

  8. Course Of Action • Two People Work on Programmed I/O • Two People Work On Ultra DMA • Finish PIO And Focus On Ultra DMA • Develop Behavioral Description To Simulate Hard Disk • Simulate And Test Our Interface

  9. Gantt Chart

  10. FinalProduct • Verilog RTL Description That Represents Ultra DMA And PIO Modules • Behavioral Description of Hard Disk Interface

  11. References • General IDE Information: http://www.pcguide.com/ref/hdd/index.htmhttp://www.hardwarecentral.com/hardwarecentral/tutorials/39/1/ • ATA5 Specification: http://www.t13.org

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