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OS-aware Tuning Improving Instruction Cache Energy Efficiency on System Workloads

OS-aware Tuning Improving Instruction Cache Energy Efficiency on System Workloads. Authors : Tao Li, John, L.K. Published in : Performance, Computing, and Communications Conference, 2006. IPCCC 2006. 25th IEEE International Date of Conference :  10-12 April 2006.

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OS-aware Tuning Improving Instruction Cache Energy Efficiency on System Workloads

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  1. OS-aware TuningImproving Instruction Cache Energy Efficiency on System Workloads Authors : Tao Li, John, L.K. Published in : Performance, Computing, and Communications Conference, 2006. IPCCC 2006. 25th IEEE International Date of Conference :  10-12 April 2006 第31組 9962111 邱鎮浩, 9962306蘇育毅, 9962145吳修億

  2. Outline 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 / 30 1.Introduction 2.Experimental Methodology 3.User/OS I-Cache Accesses Characterization 4.OS-aware I-Cache Tuning 5.Power and Performance Evaluation 6.Conclusions

  3. 1.Introduction 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 / 30 • Dynamic power dissipation • Due to charging and discharging highly capacitive bit lines and sense amps • Static power dissipation • 電晶體越做越小->自行導通

  4. 半導體規格影響耗能 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 / 30

  5. 15個app耗能表 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 / 30

  6. Dynamic省電: • OS-aware cache way lookup • Static省電: • OS-aware cache set drowsy mode 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 / 30

  7. 2.Experimental Methodology 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 / 30 Modified vision of SoftWatt SimOS OS: SGI-IRI 5.3商業版 硬體: 8-issue superscalar processor split L1 Instruct. ,data cache unified L2 cache memory 實測15個application

  8. 15個application 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 / 30 Vortex : database manipulation code Gcc : compiler code Sendmail : SMTP, 1KB~1.5MB Fileman : cp, rm, chmod, tar –cvf… …… OS activity ranges from 6% in compress,92% in fileman

  9. 3.User/OS I-Cache Accesses Characterization OSinstruc. User instruc. Dual mode 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 / 30

  10. 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 / 30

  11. OS-aware Cache Way Lookup 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 A conventional 4-way set associative cache requires four tag comparisons and four data array read-outs for a cache access. Nevertheless, during user execution, performing tag comparisons and data array read-outs for OS cache lines are unnecessary and waste extra dynamic power.

  12. OS-aware Cache Way Lookup 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 • Cache way mode bit • Processor status register(PSR)

  13. OS-aware Cache Way Lookup 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億

  14. OS-aware Cache Way Lookup 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 • Once generated, they remain unchanged unless a cache line replacement. • The processor switches mode.

  15. OS-aware Cache Way Lookup 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億

  16. OS-aware Cache Set Drowsy Mode 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 Due to CMOS technology scaling, static power due to leakage current is gaining in importance in I-cache power dissipation. These make efforts at leakage control essential to maintain control of I-cache power on current and next generations of processors.

  17. OS-aware Cache Set Drowsy Mode 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 State-preserving drowsy cache techniques.(L1) Gated-Vdd technique.(L2) Cache way mode bit

  18. OS-aware Cache Set Drowsy Mode 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億

  19. OS-aware Cache Set Drowsy Mode 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億

  20. OS-aware Cache Set Drowsy Mode 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億

  21. OS-aware Cache Set Drowsy Mode 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 Access-biased classification.

  22. OS-aware Cache Set Drowsy Mode 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億

  23. 5.Power and Performance Evaluation 合計共能省下30%的dynamic power • 使用OS-aware cache way lookup之後，dynamic power省電的比例 • user execution能省下29% • OS execution能省下30% 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 / 30

  24. 5.Power and Performance Evaluation 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 / 30 dynamic power的省電與否與cache way access的減少有關聯 OS-aware cache way lookup能省下約30%的dynamic power而不影響其效能power而不影響其效能

  25. 5.Power and Performance Evaluation 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 / 30 • 經測試之後 • Residency-based drowsy mode scheme能省下約5% - 50%的leakage power • Access-based drowsy mode scheme藉由將部分的cache設成drowsy state以減少更多的leakage power，平均約能省下37%的leakage power

  26. 5.Power and Performance Evaluation 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 / 30 • OS-aware cache set drowsy mode method執行時間會略高於正常值（<1%）因： • 誤將要用到的cache set設成drowsy mode的花費相對較低 • 套用cache set drowsy policies能讓存取drowsy cache的機率大幅降低

  27. 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 / 30

  28. 6.Conclusions 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 / 30 為了提升I-cache的用電效率，我們將從user/OS I-cache在系統執行時的存取方式著手，在dual-mode operation中觀察其省電能力

  29. 6.Conclusions 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 / 30 OS-aware cache way lookup藉由減少parallel tag comparison以及data array readout來降低dynamic power消耗 OS-aware tuning能有效地減少因CMOS製程技術進步產生的額外static power消耗 OS-aware tuning能降低dynamic power和static power的消耗的目的，且只需做少許的硬體元件更動就能達成。

  30. Thanks for your listening 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 / 30

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