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RAMP/HAsim Status Update

RAMP/HAsim Status Update. joel.emer@intel.com michael.adler@intel.com angshuman.parashar@intel.com pellauer@csail.mit.edu vmurali@csail.mit.edu. Joel Emer Michael Adler Angshuman Parashar Michael Pellauer Murali Vijayaraghavan. VSSAD Group Intel. CSG Group, CSAIL MIT.

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RAMP/HAsim Status Update

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  1. RAMP/HAsim Status Update joel.emer@intel.com michael.adler@intel.com angshuman.parashar@intel.com pellauer@csail.mit.edu vmurali@csail.mit.edu Joel Emer Michael Adler Angshuman Parashar Michael Pellauer Murali Vijayaraghavan VSSAD Group Intel CSG Group, CSAIL MIT

  2. Infrastructure Update • AWB Plug N Play • Hardware Language Support • Bluespec, VHDL, Verilog • Software Language Support • C++ • Build Procedure • Updated to scons • Automatic Parallel Build • Common data types between hardware and software • Common Platform

  3. History and Motivation XUP Model “Sim” Model Top Level Wires BDPI XUP Board LEDs and Switches (image source: xilinx.com) Software Simulator Processes (image source: intel.com)

  4. History and Motivation Platform Independent Model front_panel.writeLED() Virtual Platform XUP Front Panel “Sim” Front Panel or Top Level Wires BDPI XUP Board LEDs and Switches (image source: xilinx.com) Software Simulator Processes (image source: intel.com)

  5. Virtual Platform • Provide common set of functionalities across multiple physical platforms • XUP Board • PCI-express Board • Intel FSB Socket • Bluesim/Vsim • BEE3 • Leverage Asim Plug N Play • Minimize module replacements/recoding while moving across platforms

  6. Virtual Platform Fetch Decode Exe Timing + Functional Modules Control FuncModel Soft Connections Virtual Platform Platform Interface Virtual Devices Device 0 Device 1 Device 2 Communication Layer(s) Physical Platform

  7. Virtual Platform on XUP Fetch Decode Exe Timing + Functional Modules Control FuncModel Soft Connections Virtual Platform Platform Interface Virtual Devices Front Panel VGA Memory LEDs Switches VGA On-Board Memory

  8. Virtual Platform on Simulator Fetch Decode Exe Timing + Functional Modules Control FuncModel Soft Connections Virtual Platform Platform Interface Virtual Devices Front Panel VGA Memory UNIX Pipe Communication Layer Pipe I/O Bluesim

  9. Virtual Platform on PCIe System Fetch Decode Exe Timing + Functional Modules Control FuncModel Soft Connections Virtual Platform Platform Interface Virtual Devices Host Software Front Panel VGA Memory Communication Layer(s) PCIe-based Host System

  10. Communication with Host Software: Hybrid Modules FPGA Host Fetch Decode Decode Execute Controller Controller Func Model Front Panel Front Panel Console Console Hybrid Module Communication Layers Communication Layers PCI Express

  11. Hybrid Module Communication: The Paradigm FPGA Modules Software Modules Fetch Decode Execute Decode Controller Controller Func Model Controller Controller Server - Accept Request - Send Response Start Stop Step Start Stop Step Client - Make Request - Accept Response HAsim Remote Request/Response (RRR) PrintAssert PrintEvent PrintStat PrintAssert PrintEvent PrintStat Client Server Communication Layers Communication Layers PCI Express

  12. RRR Protocol Stack FPGA Modules Software Modules Key Issues • Service IDs • Automatic Assignment • Request and Response Types • Flexibility • Ease of Use Fetch Decode Execute Decode Controller Func Model Controller RRR Protocol Stack RRR Protocol Stack Server - Accept Request - Send Response Start Stop Step Start Stop Step Client - Make Request - Accept Response PrintAssert PrintEvent PrintStat PrintAssert PrintEvent PrintStat Client Server Low Level Driver Kernel Driver PCI Express

  13. RRR Specification Language // -------- // typedefs // -------- typedef MSG_CLASS { HOST: UINT8, FPGA: Bit#(8) }; typedef STATUS { HOST: bool, FPGA: Bool }; typedef UINT { HOST: UINT64, FPGA: Bit#(64) }; // -------------------------------------- // create a new service called CONTROLLER // -------------------------------------- service CONTROLLER { // ------------------------------------------- // declare services provided by HOST partition // ------------------------------------------- server HOST <- FPGA; { method PrintMessage(in MSG_CLASS, out STATUS); method PrintStat(in MSG_CLASS); method PrintEvent(in MSG_CLASS); }; // ------------------------------------------- // declare services provided by FPGA partition // ------------------------------------------- server FPGA <- Host; { method Start(); method Stop(); method Step(in UINT); }; };

  14. RRR Protocol Stack FPGA Modules Software Modules Fetch Decode Execute Decode Controller Func Model Controller Channel IO Channel IO CSR DMA Interrupt Interrupt CSR Hardware Channels Low Level Driver Kernel Driver

  15. RRR Protocol Stack FPGA Modules Software Modules Fetch Decode Execute Decode Controller Func Model Controller RRR Server RRR Client RRR Server RRR Client Channel 0 Channel 1 Channel 1 Channel 0 Channel IO Channel IO CSR DMA Interrupt CSR Hardware Channels Low Level Driver Kernel Driver

  16. RRR Protocol Stack FPGA Modules Software Modules 1 1 Fetch Decode Execute Decode rrr_service_ids.bsv `define CONTROLLER_SERVICE_ID 0 `define DECODE_SERVICE_ID 1 `define MEMORY_SERVICE_ID 2 `define NUM_SERVICES 3 RRR specification files 0 0 Controller Func Model Controller SID 0 SID 1 RRR Server RRR Client RRR Server RRR Client Channel 0 Channel 1 Channel 1 Channel 0 Channel IO Channel IO CSR DMA Interrupt CSR Hardware Channels Low Level Driver Kernel Driver

  17. RRR Protocol Stack FPGA Modules Software Modules 1 1 Fetch Decode Execute Decode RRR specification files 0 0 Controller Func Model Controller Stub Stub SID 0 SID 1 RRR Server RRR Client RRR Server RRR Client Channel 0 Channel 1 Channel 1 Channel 0 Channel IO Channel IO CSR DMA Interrupt CSR Hardware Channels Low Level Driver Kernel Driver

  18. Stub Stub SID 0 SID 1 RRR Protocol Stack FPGA Modules Software Modules 1 1 Fetch Decode Execute Decode 0 0 Controller Func Model Controller Stub Stub SID 0 SID 1 RRR Server RRR Client RRR Server RRR Client Channel 0 Channel 1 Channel 1 Channel 0 Channel IO Channel IO CSR DMA Interrupt CSR Hardware Channels Low Level Driver Kernel Driver

  19. Stub Stub SID 0 SID 1 Switching Physical Platforms FPGA Modules Software Modules 1 1 Fetch Decode Execute Decode 0 0 Controller Func Model Controller Stub Stub SID 0 SID 1 RRR Server RRR Client RRR Server RRR Client Channel 0 Channel 1 Channel 1 Channel 0 Channel IO Channel IO CSR DMA Interrupt CSR Hardware Channels Low Level Driver Kernel Driver

  20. Stub Stub SID 0 SID 1 PCIe-based Physical Platform FPGA Modules Software Modules 1 1 Fetch Decode Execute Decode 0 0 Controller Func Model Controller Stub Stub SID 0 SID 1 RRR Server RRR Client RRR Server RRR Client Channel 0 Channel 1 Channel 1 Channel 0 Channel IO Channel IO CSR DMA Interrupt CSR Hardware Channels Low Level Driver Kernel Driver

  21. Stub Stub SID 0 SID 1 Simulation Physical Platform FPGA Modules Software Modules 1 1 Fetch Decode Execute Decode 0 0 Controller Func Model Controller Stub Stub SID 0 SID 1 RRR Server RRR Client RRR Server RRR Client Channel 0 Channel 1 Channel 1 Channel 0 Channel IO Channel IO BDPI Layer UNIX inter-process communication

  22. Dictionaries // append to STATDEFS.bsh, STATDEFS.h def STAT.BRANCHES_MISPREDICTED "mispredicted branches = "; // append to EVENTDEFS.bsh, EVENTDEFS.h def EVENT.SIM_FAILED "simulation failed"; // append to TRACEDEFS.bsh, TRACEDEFS.h def TRACE.FETCH "fetch instruction %d"; // note: 1 param def TRACE.DECODE "decode inst %d into %d"; // note: 2 params

  23. Infrastructure Summary FPGA Modules Software Modules Fetch Decode Exe Memory Front Panel Control FuncModel Decode Virtual Platform Platform Interface Front Panel Memory RRR Client + Server RRR Client + Server Channel IO Channel IO Hardware Software

  24. Conclusion • Virtual Platform • Multi-layered set of abstractions providing platform-independent interfaces to platform-dependent devices • Remote Request/Response • Part of the Virtual Platform hierarchy • Facilitates communication between multiple partitions of hybrid modules • Tedious HDL plumbing code is auto-generated from specification files

  25. Backup Slides

  26. Sample RRR Service Stub

  27. Outline • History and Motivation • Virtual Platforms • Hybrid Modules and RRR • Conclusion and Demo

  28. Hybrid Modules FPGA Modules Software Modules Fetch Decode Exe Memory Front Panel Control FuncModel Decode Virtual Platform HAsim Remote Request/Response (RRR) Platform Interface Front Panel Memory RRR Client + Server RRR Client + Server Channel IO Channel IO Hardware Software

  29. RRR: Intel FSB FPGA Modules Software Modules Fetch Decode Exe Memory Front Panel Control FuncModel Decode Virtual Platform Platform Interface Front Panel Memory RRR Client + Server RRR Client + Server Channel IO Channel IO FSB Driver Hardware Software

  30. RRR: Simulator FPGA Modules Software Modules Fetch Decode Exe Memory Front Panel Control FuncModel Decode Virtual Platform Platform Interface Front Panel Memory RRR Client + Server RRR Client + Server Channel IO UNIX pipe Channel IO Hardware Software

  31. Hybrid Modules • Hybrid Modules • Primary points of communication between FPGA and Host Software • Module functionality can be split between FPGA and software • How do partitions of a hybrid module communicate with each other?

  32. Hybrid Modules (cont.) • Module definition • hybrid_fetch_unit.awb %sources –t BSV –v PUBLIC hardware_fetch_unit.bsv %sources –t CPP –v PUBLIC software_fetch_unit.h %sources –t CPP –v PRIVATE software_fetch_unit.cpp • Build process • Collects BSVs and generates “hardware” bitfile or simulation binary • Collects CPPs and generates “software” binary • Runtime • Software binary loads bitfile onto FPGA, or forks off simulation “hardware” binary • Software Controller sends “start” RRR request to Hardware Controller

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