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PROOFS: A Fault Simulation Algorithm

PROOFS: A Fault Simulation Algorithm. Pratap S.Prasad ELEC 7250 Instructor: Prof. Vishwani Agrawal. Fault Simulation. Fault Simulation Simulators Necessity Strategy Need For : Speed Memory Reduction. Related Work. Fault simulation strategies Approximate methods

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PROOFS: A Fault Simulation Algorithm

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  1. PROOFS: A Fault Simulation Algorithm Pratap S.Prasad ELEC 7250 Instructor: Prof. Vishwani Agrawal Prasad: ELEC7250

  2. Fault Simulation • Fault Simulation • Simulators • Necessity • Strategy • Need For : • Speed • Memory Reduction Prasad: ELEC7250

  3. Related Work • Fault simulation strategies • Approximate methods • Statistical Fault Analysis • Critical Path Tracing • Accurate methods • Concurrent • Deductive • Differential • Parallel • Others Prasad: ELEC7250

  4. PROOFS Algorithm • PROOFS : Parallel RestOrative Order-independent Fault Simulator • A hybrid of the concurrent, differential, and parallel fault simulation algorithms. For every test vector { Do true-value simulation; for every undetected faulty machine { Give a unique simulation ID; Inject current fault; recover current states; do event-driven simulation; if the fault is detected, drop the fault; } } Prasad: ELEC7250

  5. Results • PROOFS algorithm was run on many of the ISCAS sequential benchmark circuits • A comparison of the two algorithms shows the PROOFS is 6 to 67 times faster than the concurrent algorithm while always requiring less memory. • Memory is reduced by up to 7.5 times over the concurrent algorithm • Sample Comparisons: Prasad: ELEC7250

  6. Conclusion • PROOFS – A very fast fault simulation algorithm • The new techniques in PROOFS are: • Use of group-id to avoid the overhead of restoring the good values after each fault propagation • Concept of active and inactive faults to prevent eventless fault simulation • Efficient method of fault injection by circuit modification • An efficient fault ordering to minimize events in word parallel operations. It has been shown that this algorithm is 6.6 to 67 times faster than a state of the art concurrent fault simulator while also requiring much less memory. Prasad: ELEC7250

  7. References • M.L.Bushnell and V.D.Agrawal,”’Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI circuits”’ Kluwer Academic Publishers., 2000 • M.Abramovici, M.A.Breuer, A.D.Friedman,”’Digital Systems Testing and Testable Design”’, IEEE Press, 1995. • W.-T.Cheng and J.H.Patel, PROOFS: A super fast simulator for sequential circuits, Design Automation Conference, Mar. 1990. • T.M.Niermann, Wu-Tung Cheng and J.H. Patel”’Proofs: a fast, memory efficient sequential circuit fault simulator”’, Proceedings of the 27th ACM/IEEE conference on Design automation, pp. 535 - 540, 1991 Prasad: ELEC7250

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