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Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. Semiconductor Memories. December 20, 2002. Chapter Overview. Memory Classification. Memory Architectures. The Memory Core. Periphery. Reliability Case Studies.
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Digital Integrated CircuitsA Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Semiconductor Memories December 20, 2002
Chapter Overview • Memory Classification • Memory Architectures • The Memory Core • Periphery • Reliability • Case Studies
Semiconductor Memory Classification Non-Volatile Read-WriteMemory Read-Write Memory Read-Only Memory Random Non-Random EPROM Mask-Programmed Access Access 2 E PROM Programmable (PROM) FLASH FIFO SRAM LIFO DRAM Shift Register CAM
Decoder reduces the number of select signals K = log N 2 Memory Architecture: Decoders M bits M bits S S 0 0 Word 0 Word 0 S 1 Word 1 Word 1 A 0 S Storage Storage 2 Word 2 Word 2 A cell cell 1 words A N K 1 Decoder 2 S N 2 2 Word N 2 Word N 2 2 2 S N 1 2 Word N 1 Word N 1 2 2 K log N 5 2 Input-Output Input-Output ( M bits) ( M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals
Clock -address -address Z X generator buffer buffer Predecoder and block selector Bit line load Transfer gate Column decoder Sense amplifier and write driver CS, WE I/O x1/x4 -address -address Y X buffer buffer controller buffer buffer Block Diagram of 4 Mbit SRAM 128 K Array Block 0 Subglobal row decoder Subglobal row decoder Global row decoder Block 30 Block 31 Block 1 Local row decoder [Hirose90]
Read-Only Memory Cells BL BL BL VDD WL WL WL 1 BL BL BL WL WL WL 0 GND Diode ROM MOS ROM 1 MOS ROM 2
MOS OR ROM BL [0] BL [1] BL [2] BL [3] WL [0] V DD WL [1] WL [2] V DD WL [3] V bias Pull-down loads
MOS NOR ROM V DD Pull-up devices WL [0] GND WL [1] WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3]
MOS NOR ROM Layout Cell (9.5l x 7l) Programmming using the Active Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion
MOS NOR ROM Layout Cell (11l x 7l) Programmming using the Contact Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion
MOS NAND ROM V DD Pull-up devices BL [0] BL [1] BL [2] BL [3] WL [0] WL [1] WL [2] WL [3] All word lines high by default with exception of selected row
No contact to VDD or GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM MOS NAND ROM Layout Cell (8l x 7l) Programmming using the Metal-1 Layer Only Polysilicon Diffusion Metal1 on Diffusion
NAND ROM Layout Cell (5l x 6l) Programmming using Implants Only Polysilicon Threshold-alteringimplant Metal1 on Diffusion
V DD BL r word WL C bit c word Equivalent Transient Model for MOS NOR ROM Model for NOR ROM • Word line parasitics • Wire capacitance and gate capacitance • Wire resistance (polysilicon) • Bit line parasitics • Resistance not dominant (metal) • Drain and Gate-Drain capacitance
Equivalent Transient Model for MOS NAND ROM V DD Model for NAND ROM BL C L r bit c bit r word WL c word • Word line parasitics • Similar to NOR ROM • Bit line parasitics • Resistance of cascaded transistors dominates • Drain/Source and complete gate capacitance
Precharged MOS NOR ROM V f DD pre Precharge devices WL [0] GND WL [1] WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3] PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design.
D G S Non-Volatile MemoriesThe Floating-gate transistor (FAMOS) Floating gate Gate Source Drain t ox t ox + +_ n n p Substrate Schematic symbol Device cross-section
20 V 0 V 5 V 20 V 0 V 5 V 10 V 5 V 5 V 2.5 V 2 2 S D S D S D Avalanche injection Removing programming voltage leaves charge trapped Programming results in higher V . T Floating-Gate Transistor Programming
FLOTOX EEPROM Gate Floating gate I Drain Source V 20 – 30 nm -10 V GD 10 V 1 1 n n Substrate p 10 nm Fowler-Nordheim I-V characteristic FLOTOX transistor
V DD EEPROM Cell BL WL Absolute threshold control is hard Unprogrammed transistor might be depletion 2 transistor cell
Flash EEPROM Control gate Floating gate erasure Thin tunneling oxide 1 1 n source n drain programming p- substrate Many other options …
Cross-sections of NVM cells Flash EPROM Courtesy Intel
Select transistor Word lines Active area STI Bit line contact Source line contact NAND Flash Memory Courtesy Toshiba
Read-Write Memories (RAM) • STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential • DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended
Q 6-transistor CMOS SRAM Cell WL V DD M M 2 4 Q M M 6 5 M M 1 3 BL BL
CMOS SRAM Analysis (Read) WL V DD M BL 4 BL Q 0 = M Q 1 = 6 M 5 V V V M DD DD DD 1 C C bit bit
CMOS SRAM Analysis (Read) 1.2 1 0.8 0.6 Voltage Rise (V) 0.4 0.2 Voltage rise [V] 0 0 0.5 1 1.2 1.5 2 2.5 3 Cell Ratio (CR)
WL V DD M 4 M Q 0 = 6 M 5 Q 1 = M 1 V DD BL 1 BL 0 = = CMOS SRAM Analysis (Write)
VDD M2 M4 Q Q M1 M3 GND M5 M6 WL BL BL 6T-SRAM — Layout
Static power dissipation -- Want R large L Bit lines precharged to V to address t problem DD p Resistance-load SRAM Cell WL V DD R R L L Q Q M M 3 4 BL BL M M 1 2
BL 1 BL 2 WWL WWL RWL RWL M 3 V V X M X 2 DD T 1 M 2 V DD BL 1 C S V D BL 2 V V 2 DD T No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = V -V WWL Tn 3-Transistor DRAM Cell
BL2 BL1 GND RWL M3 M2 WWL M1 3T-DRAM — Layout
V V (1) BL V PRE D V (1) V (0) t Sense amp activated Word line activated Sense Amp Operation
Metal word line SiO 2 Poly Field Oxide Diffused + + n n bit line Inversion layer Poly Polysilicon induced by Polysilicon plate plate bias gate 1-T DRAM Cell Capacitor M word 1 line Cross-section Layout Uses Polysilicon-Diffusion Capacitance Expensive in Area
Advanced 1T DRAM Cells Word line Capacitor dielectric layer Cell plate Insulating Layer Cell Plate Si Transfer gate Isolation Refilling Poly Capacitor Insulator Storage electrode Storage Node Poly Si Substrate 2nd Field Oxide Stacked-capacitor Cell Trench Cell
Bit Bit Bit Bit Bit Bit Word M8 M9 M4 M5 CAM ••• CAM M6 M7 Word S S Word int CAM ••• CAM M3 M2 Match M1 Wired-NOR Match Line Static CAM Memory Cell ••• •••
CAM in Cache Memory CAM SRAM ARRAY ARRAY Hit Logic Address Decoder Input Drivers Sense Amps / Input Drivers Address Tag Hit R/W Data
Periphery • Decoders • Sense Amplifiers • Input/Output Buffers • Control / Timing Circuitry
Row Decoders Collection of 2M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder
Hierarchical Decoders Multi-stage implementation improves performance • • • WL 1 WL 0 A A A A A A A A A A A A A A A A 0 1 0 1 0 1 0 1 2 3 2 3 2 3 2 3 • • • NAND decoder using 2-input pre-decoders A A A A A A A A 1 0 0 1 3 2 2 3
V DD V DD V DD V DD Dynamic Decoders Precharge devices GND GND WL 3 WL 3 WL 2 WL 2 WL 1 WL 1 WL 0 WL 0 V A A A A f DD 0 0 1 1 A A A A f 0 0 1 1 2-input NAND decoder 2-input NOR decoder
BL BL BL BL 0 1 2 3 S 0 A 0 S 1 S 2 A S 1 3 D 4-input pass-transistor based column decoder 2-input NOR decoder Advantages: speed (tpd does not add to overall memory access time) Only one extra transistor in signal path Disadvantage: Large transistor count
4-to-1 tree based column decoder BL BL BL BL 0 1 2 3 A 0 A 0 A 1 A 1 D Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders Solutions: buffers progressive sizing combination of tree and pass transistor approaches
V V V V V V DD DD DD DD DD DD WL WL WL 0 1 2 f f f f f f • • • R R R f f f f f f V DD Decoder for circular shift-register
D make V as small × D C V as possible t = ---------------- p I av large small Sense Amplifiers Idea: Use Sense Amplifer small s.a. transition input output