Timing Measurements of Synchronization Circuits

1. Timing Measurements of Synchronization Circuits Yaron Semiat and Ran Ginosar Technion, Israel With help from Charles Dike (Intel)

2. Outline • Why measure • Measuring basics • Setup • Synchronous operation • Metastability • The two-FF synchronizer • Multi-Sync Clock Domains • Definitions • Architectures and Measurements • Comparison • Conclusions

3. Why Measure? • Validate synchronizers • Synchronizers may elude simulations • Formal verification is a challenge • Characterize synchronization circuits • Measure t and TW in • Compare Synchronizers • Educate

4. Measuring Basics • Why measure • Measuring basics • Setup • Synchronous operation • Metastability • The two-FF synchronizer • Multi-Sync Clock Domains • Definitions • Architectures and Measurements • Comparison • Conclusions

5. FPGA: Easy testing Standard cell designfor ASIC and SoC Output  Trigger Catch only actual events Measure DT(Output – Clock) Special scope Computer controlled OUTPUT TRIGGER 25.2 MHz FPGA Scope 25.175 MHz CLOCK INPUT Measurement Setup

6. Measuring Basics • Why measure • Measuring basics • Setup • Synchronous operation • Metastability • The two-FF synchronizer • Multi-Sync Clock Domains • Definitions • Architectures and Measurements • Comparison • Conclusions

7. TRIGGER D Q D Q FF FF Scope 25.175 MHz CLOCK INPUT Synchronous Operation • Baseline • Setup validation

8. Synchronous Waveform

9. ALIGN PROJECT 120 - 100 - 80 - 60 - 40 - 20 0 20 40 60 80 Processing • Align all rows along peak • Add all rows • Normalize the data • Axes: # of events vs. DT • Collect over time • Typically 20 minutes to 6 hours

10. Synchronous sampling flip-flop 1000000 100000 10000 Frequency 1000 100 10 1 -15 -10 -5 0 5 10 15 Relative flip-flop propagation delay (ps) Synchronous Sampling

11. Two clocks enter the FPGA Only one clock employed FPGA clock nets are not optimized Jitter is < 200ps Maybe OK for slow FPGA applications Clock cross-talk noise

12. Measuring Basics • Why measure • Measuring basics • Setup • Synchronous operation • Metastability • The two-FF synchronizer • Multi-Sync Clock Domains • Definitions • Architectures and Measurements • Comparison • Conclusions

13. D Q FF And now to our main feature presentation! Metastability Demonstration 25.2 MHz TRIGGER Scope 25.175 MHz INPUT

14. Metastability ( FF on FPGA )

15. TW t Measuring t and TW

16. Measuring Basics • Why measure • Measuring basics • Setup • Synchronous operation • Metastability • The two-FF synchronizer • Multi-Sync Clock Domains • Definitions • Architectures and Measurements • Comparison • Conclusions

17. Output has ~150ps jitter but is stable The Two-FF Synchronizer • Reference for other synchronizers Synchronized data FF FF data clock

18. Synchronizing Multisync Domains • Why measure • Measuring basics • Setup • Synchronous operation • Metastability • The two-FF synchronizer • Multi-Sync Clock Domains • Definitions • Architectures and Measurements • Comparison • Conclusions

19. Relations of Two Clock Domains

20. Cost-Performance Trade-off

21. 25.175 MHz 25.2 MHz Multi-Sync Test Setup • Data alternates 0,1,0,… • Last FF represents the receiver • Compare synchronizer—internals and output • Test is plesiochronous  multi-sync TRIGGER FF FF SYNC Scope INPUT

22. Synchronizing Multisync Domains • Why measure • Measuring basics • Setup • Synchronous operation • Metastability • The two-FF synchronizer • Multi-Sync Clock Domains • Definitions • Architectures and Measurements • Comparison • Conclusions

23. Data delayed to avoid conflict Home-in on either0° (avoid), or 180° (snap) Adaptation:Clear and increment Adaptation when? Continuous / Training Session Data Delay Synchronizer BUNDLED DATA SYNC DATA DIGITAL DELAY LINE CLEAR DELAYED TCLK INCREMENT SYNC conflict CONFLICT FSM detect RCLK CONFLICT_180 SYNC conflict detect

24. SYNC SYNC Data Delay Synchronizer REG DIGITAL DELAY LINE conflict FSM detect conflict detect Data-delay-sync works, but it’s expensive…

25. Dike’s Conflict Detector D_TCLK R1 G1 ME G2 R2 d conflict R1 G1 ME d RCLK G2 R2 d d RCLK conflict region

26. Dally’s Conflict Detector TCLK conflict D Q D Q E E Late d RCLK D Q E Done Waiting Early RCLK T- d Sample d d Depends on T ! RCLK conflict region

27. Which Conflict Detector? • Dike’s is more flexible: • Does not depend on knowing the clock frequency at design time • Suitable for a very wide range of frequencies

28. Clock Delay Synchronizer REG DATA TCLK SYNC conflict detector 0 1 RCLK tKO tKO d d RCLK conflict region

29. Clock Delay Synchronizer REG REG conflict detector 0 1 Clock-delay-sync is the simplest one!

30. Pointer FIFO Synchronizer DATA REG TCLK DATA_SYNC REG REG inc clock delay inc T sync pointer R pointer RCLK Fifo-sync is expensive…

31. Data sampled at 4 phases Data shifted while deciding which to use Lots of hardware & latency Source: Xilinx App Note 255 A Complex Synchronizer shift reg DATA_SYNC shift reg FF shift reg shift reg edge detect DATA REG REG RCLK0 edge detect REG REG RCLK90 decision logic edge detect REG REG 5 cycles !! edge detect REG REG

32. Synchronizing Multisync Domains • Why Measure • Measuring Basics • Setup • Synchronous operation • Metastability demonstration • The movie • The two-FF synchronizer • Multi-Sync Clock Domains • Definitions • Architectures and measurements • Comparison • Conclusions

33. Comparing the Synchronizers

34. Conclusions • Measuring synchronizers builds insight • Measurement helps determine t, TW and MTBF • With measurements, we have shown that complex synchronizers don’t work any better than simple ones…

35. Thank You!

36. ME Circuit R1 G1 O1 O2 G2 R2