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CS 230: Computer Organization and Assembly Language

CS 230: Computer Organization and Assembly Language. Aviral Shrivastava. Department of Computer Science and Engineering School of Computing and Informatics Arizona State University. Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary Jane Irwin, PSU, Ande Carle, UCB. Announcements.

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CS 230: Computer Organization and Assembly Language

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  1. CS 230: Computer Organization and Assembly Language Aviral Shrivastava Department of Computer Science and Engineering School of Computing and Informatics Arizona State University Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary Jane Irwin, PSU, Ande Carle, UCB

  2. Announcements • Project 3 • Due October 19, 2009 • Midterm • Thursday, October 22, 2009 • Contents • MIPS ISA and Programming • Function calls and register conventions • Assembling MIPS Instructions • 2’s complement number system • FP number system • Finals • Tuesday, Dec 08, 2009

  3. Computer Organization • We have leaned the ISA of the processor till now • Given an algorithm, express it in terms of the processor ISA software Instruction Set Architecture hardware

  4. Below the Program • High-level language program (in C) • swap (int v[], int k) • . . . • Assembly language program (for MIPS) • swap: sll $2, $5, 2 • add $2, $4, $2 • lw $15, 0($2) • lw $16, 4($2) • sw $16, 0($2) • sw $15, 4($2) • jr $31 • Machine (object) code (for MIPS) • 000000 00000 00101 0001000010000000 • 000000 00100 00010 0001000000100000 • 100011 00010 01111 0000000000000000 • 100011 00010 10000 0000000000000100 • 101011 00010 10000 0000000000000000 • 101011 00010 01111 0000000000000100 • 000000 11111 00000 0000000000001000 C - Compiler Assembler

  5. Working of Computer Processor Devices Control Input Memory Datapath Output

  6. Input Device Inputs Object Code 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000 Processor Devices Control Input Memory Datapath Output

  7. Object Code Stored in Memory Memory Processor Devices 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000 Control Input Datapath Output

  8. Processor Fetches an Instruction Processor fetches an instruction from memory Memory Processor Devices 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000 Control Input Datapath Output

  9. Control Decodes the Instruction Control decodes the instruction to determine what to execute Processor Devices Control 00000000100000100001000000100000 Memory Input Datapath Output

  10. Datapath Executes the Instruction Datapath executes the instruction as directed by control Processor Devices Control 00000000100 000100001000000100000 Memory Input Datapath contents Reg #4 ADD contents Reg #2 results put in Reg #2 Output

  11. Update the PC, and continue Memory Processor Devices 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000 Control Input Datapath Output Fetch Execute Decode

  12. Output Data Stored in Memory At program completion the data to be output resides in memory Memory Processor Devices Control Input 00000100010100000000000000000000 00000000010011110000000000000100 00000011111000000000000000001000 Datapath Output

  13. Output Device Outputs Data Processor Devices Control Input Memory Datapath Output 00000100010100000000000000000000 00000000010011110000000000000100 00000011111000000000000000001000

  14. MIPS ISA to Implement • Arithmetic Instructions • Add, sub, AND, OR, and slt (R-type) • Memory access instructions • LW, and SW (I-type) • Branch instructions • Beq (I-type) • Jump instructions • J (J-type)

  15. MIPS Machine Instr[25-0] 1 Shift left 2 28 32 26 0 PC+4[31-28] 0 Add Add 1 4 Shift left 2 PCSrc Jump ALUOp Branch MemRead Instr[31-26] Control Unit MemtoReg MemWrite ALUSrc RegWrite RegDst ovf Instr[25-21] Read Addr 1 Instruction Memory Read Data 1 Address Register File Instr[20-16] zero Read Addr 2 Data Memory Read Address PC Instr[31-0] 0 Read Data 1 ALU Write Addr Read Data 2 0 1 Write Data 0 Instr[15 -11] Write Data 1 Instr[15-0] Sign Extend ALU control 16 32 Instr[5-0]

  16. Build a MIPS Processor 32 32 • Today – Build the ALU • Support all the Arithmetic/Logic operations ALU control lines a ALU 32 result b

  17. ALUOp and ALU control bits

  18. Implementation Truth table for 4 ALU control bits

  19. Building a 1-bit Binary Adder carry_in A 1 bit Full Adder S = A xor B xor carry_in carry_out = (A and B) or (A and carry_in) or (B and carry_in) S B carry_out • How can we use it to build a 32-bit adder? • How can we modify it easily to build an adder/subtractor?

  20. Building 32-bit Adder c0=carry_in A0 1-bit FA S0 B0 c1 A1 1-bit FA S1 B1 c2 A2 1-bit FA S2 B2 c3 . . . c31 A31 1-bit FA S31 B31 c32=carry_out • Just connect the carry-out of the least significant bit FA to the carry-in of the next least significant bit and connect . . . • Ripple Carry Adder (RCA) • advantage: simple logic, so small (low cost) • disadvantage: slow and lots of glitching (so lots of energy consumption)

  21. Building 32-bit Adder/Subtractor c0=carry_in A0 1-bit FA S0 c1 control (0=add,1=subt) A1 1-bit FA B0 if control = 0, !B0 if control = 1 S1 B0 c2 A2 1-bit FA S2 c3 . . . c31 A31 1-bit FA S31 c32=carry_out add/subt • Remember 2’s complement is just • complement all the bits • add a 1 in the least significant bit B0 B1 B2 A 0111  0111 B - 0110+ 1010 B31

  22. Logic Operations • Logic operations operate on individual bits of the operand. $t2 = 0…0 0000 1101 0000 $t1 = 0…0 0011 1100 0000 and $t0, $t1, $t2 $t0 = or $t0, $t1, $t2 $t0 = xor $t0, $t1, $t2 $t0 = nor $t0, $t1, $t2 $t0 = • How do we expand our FA design to handle the logic operations - and, or, xor, nor ? 0…0 0000 1100 0000 0…0 0011 1101 0000 0…0 0011 0001 0000 1…1 1100 0010 1111

  23. A Simple ALU Cell add/subt carry_in op A result 1-bit FA B add/subt carry_out

  24. Tailoring the ALU to the MIPS ISA • Need to support the set-on-less-than instruction (slt) • remember: slt is an arithmetic instruction • produces a 1 if rs < rt and 0 otherwise • use subtraction: (a - b) < 0 implies a < b • Need to support test for equality (beq) • use subtraction: (a - b) = 0 implies a = b • Need to add the overflow detection hardware

  25. Modifying the ALU Cell for slt less add/subt carry_in op A result 1-bit FA B add/subt carry_out

  26. ALU for slt A0 result0 B0 + less A1 result1 B1 + 0 less . . . A31 result31 B31 + less 0 set • First perform a subtraction • Make the result 1 if the subtraction yields a negative result • Make the result 0 if the subtraction yields a positive result • tie the most significant sum bit (sign bit) to the low order less input

  27. ALU for Zero zero . . . op add/subt A0 result0 • First perform subtraction • Insert additional logic to detect when all result bits are zero B0 + less A1 result1 B1 + 0 less . . . A31 • Note zero is a 1 when result is all zeros result31 B31 + 0 less set

  28. Overflow Detection 0 1 1 1 1 0 0 1 1 1 7 1 1 0 0 –4 + 0 0 1 1 3 + 1 0 1 1 – 5 1 0 1 0 0 1 • Overflow: the result is too large to represent in the number of bits allocated • On your own: Prove you can detect overflow by: • Carry into MSB xor Carry out of MSB – 6 1 1 7

  29. Modifying the ALU for Overflow op overflow add/subt A0 result0 • Modify the most significant cell to determine overflow output setting • Disable overflow bit setting for unsigned arithmetic B0 + less A1 result1 B1 zero + . . . 0 less . . . A31 result31 + B31 0 less set

  30. Shift Operations 000000 00000 10000 01010 01000 000000 000000 00000 10000 01010 01000 000010 op rs rt rd shamt funct • Also need operations to pack and unpack 8-bit characters into 32-bit words • Shifts move all the bits in a word left or right sll $t2, $s0, 8 #$t2 = $s0 << 8 bits srl $t2, $s0, 8 #$t2 = $s0 >> 8 bits • Such shifts are logical because they fill with zeros

  31. Shift Operations 000000 00000 10000 01010 01000 000011 • An arithmetic shift (sra) maintain the arithmetic correctness of the shifted value (i.e., a number shifted right one bit should be ½ of its original value; a number shifted left should be 2 times its original value) • so sra uses the most significant bit (sign bit) as the bit shifted in • note that there is no need for a sla when using two’s complement number representation sra $t2, $s0, 8 #$t2 = $s0 >> 8 bits • The shift operation is implemented by hardware (usually a barrel shifter) outside the ALU

  32. MIPS Machine Instr[25-0] 1 Shift left 2 28 32 26 0 PC+4[31-28] 0 Add Add 1 4 Shift left 2 PCSrc Jump ALUOp Branch MemRead Instr[31-26] Control Unit MemtoReg MemWrite ALUSrc RegWrite RegDst ovf Instr[25-21] Read Addr 1 Instruction Memory Read Data 1 Address Register File Instr[20-16] zero Read Addr 2 Data Memory Read Address PC Instr[31-0] 0 Read Data 1 ALU Write Addr Read Data 2 0 1 Write Data 0 Instr[15 -11] Write Data 1 Instr[15-0] Sign Extend ALU control 16 32 Instr[5-0]

  33. Yoda says… Use your feelings, Obi-Wan, and find him you will

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