Single Cycle Processor

1. Single Cycle Processor Instr[25-0] 1 Shift left 2 28 32 26 0 PC+4[31-28] 0 Add Add 1 4 Shift left 2 PCSrc Jump ALUOp Branch MemRead Instr[31-26] Control Unit MemtoReg MemWrite ALUSrc RegWrite RegDst ovf Instr[25-21] Read Addr 1 Instruction Memory Read Data 1 Address Register File Instr[20-16] zero Read Addr 2 Data Memory Read Address PC Instr[31-0] 0 Read Data 1 ALU Write Addr Read Data 2 0 1 Write Data 0 Instr[15 -11] Write Data 1 Instr[15-0] Sign Extend ALU control 16 32 Instr[5-0]

2. Setting of the control signals

3. Add two instructions to the existing data path and control From the previous slides, we learn that the processor does not have i-type instructions, and others included in the design. Now we like to add two instructions which are addiu, sltiu addiu $rt, $rs, imm; $rt = $rs + imm; example such as addiu $12, $10, 250 sltiu $rt, $rs, imm; $rt = 1 if $rs < imm; example such as sltiu $1, $2, 100 Now we check (1) Data path, what functional blocks are need in the data path to execute this instruction(2) set the control signals properly to select the right inputs for ALU and right selection signals for MUXes used in the data path.

4. MDR The Multicycle Datapath with Control Signals PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

6. Control signals Input values are states states

7. From the multi-cycle processor data path and control, and the state transition diagram, we like to add two more instructions to the existing design Now we like to add two instructions which are addiu, sltiu addiu $rt, $rs, imm; $rt = $rs + imm; example such as addiu $12, $10, 250 sltiu $rt, $rs, imm; $rt = 1 if $rs < imm; example such as sltiu $1, $2, 100 Now we check (1) Data path, what functional blocks are need in the data path to execute this instruction(2) set the control signals properly to select the right inputs for ALU and right selection signals for MUXes used in the data path. It is not as straight forward as the single cycle processor case. We need to modify the state transition diagram to include i-type instructions, then design the control signals according to the state. Suggested answer: add state 10, state 11 for i-type instructions, then assert proper control signals for state 10 and state 11. you may need more states depending on your design.

13. A Pipelined Processor

14. Control Signals In the table above Add a row for addiu Add a row for sltiu

15. addiu $1, $2, 100 sltiu $3, $1, 200; we have data dependence RAW hazard due to $1 addiu $1, $2, 100 sltiu $1, $2, 100; Do we have data hazards here? If yes, can we solve this hazard by forwarding. lw $7, 0($10) add $8, $7, $9; Do we have data hazards here? If yes, can we solve this hazard by forwarding.