A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits

1. A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits Duc Anh Tran • A. Virazel A. Bosio L. Dilillo P. Girard S. Pravossoudovitch • Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier • Université Montpellier 2 – CNRS • H-J. Wunderlich • Institut fürTechnischeInformatik – Universität Stuttgart • tran@lirmm.fr South European Test Seminar – March 2011

2. Research motivation • Circuit robustness • Fault tolerant architectures • Hybrid fault tolerant architecture • Comparison with TMR • Conclusion Outline South European Test Seminar – March 2011

3. CMOS evolution Circuit robustness  Enable the use of future CMOS technology nodes Research motivation South European Test Seminar – March 2011 High manufacturing defect density Realization of complex systems Reduction of the manufacturing cost Optimization of performances and power dissipation Vulnerability of circuits with regard to soft and timing errors

4. Process variations Timing error Aging phenomenon Manufacturing defects Permanent error Cosmic radiations EM interferences Soft error Redundant resources • Time • Information • Hardware Digital circuits Circuit robustness South European Test Seminar – March 2011

5. Information redundancy: Code detection/correction • Time redundancy: Re-computation • Hardware redundancy: Duplication, triplication • Low area overhead expected for regular structures (memories) Not adapted for logic circuits • Low area overhead • Low power consumption * High delay penalty Tolerate only soft errors • Hard errors tolerance High area overhead High power consumption Fault tolerant architectures South European Test Seminar – March 2011

6. Process variations Timing error Aging phenomenon Manufacturing defects Permanent error Cosmic radiations EM interferences Soft error Redundant resources • Time • Error correction • Hardware • Permanent defect • tolerance • Information • Error detection Digital circuits Fault tolerant architectures South European Test Seminar – March 2011

7. CLK • Soft and timing redundancies Register Register Logic circuit inputs outputs enable OK enable Information redundancy Hybrid fault tolerance architecture South European Test Seminar – March 2011

8. Information redundancy: Parity predictor synthesis XOR tree Parity predictor Logic circuit PIs PIs Parity bits POs + Synthesis + + + + Parity bits Hybrid fault tolerance architecture South European Test Seminar – March 2011

9. Area overhead of parity predictor with regard to LC • Circuit: Iscas85 • Synthesize tool: Cadence RTL Compiler • Code: Simple parity (1 bit) Hybrid fault tolerance architecture South European Test Seminar – March 2011

10. CLK • Information redundancy: Duplication instead of code prediction Register Register outputs Logic circuit inputs • Lower area overhead • Better error detection Logic circuit enable enable = Hybrid fault tolerance architecture South European Test Seminar – March 2011

11. CLK Register Register • Permanent error tolerance LC 1 MUX IN MUX OUT • Fault free operation • 2 LCs active • 3rd LC in stand by LC 2 = • 3 configurations, selected by FSM Error detected Re-compute the last input LC 3 enable enable Change configuration to get rid of hard errors FSM1: after 2 consecutive errors FSM2: at each error FSM CLK Hybrid fault tolerance architecture South European Test Seminar – March 2011

12. CUT 1-2 FSM 1 When an error is detected for the 1st time, we repeat the same configuration. If an error is detected again for the same configuration, we switch to the next configuration. CUT 3-1 CUT 2-3 Hybrid fault tolerance architecture South European Test Seminar – March 2011

13. CUT 1-2 FSM 2 Each time an errorisdetected, weswitch the config. If 6 errorsconsecutives are detected for the samevector, we stop everything. CUT 3-1 CUT 2-3 Hybrid fault tolerance architecture South European Test Seminar – March 2011

14. Example FSM1 FSM2 Hybrid fault tolerance architecture South European Test Seminar – March 2011

15. Area overhead in term of transistor count Comparison with TMR South European Test Seminar – March 2011

16. Power consumption Comparison with TMR South European Test Seminar – March 2011

17. Aging • Only 2 LCs run in parallel  less aging than TMR • Possibility to change configurations in order to keep balance aging Comparison with TMR South European Test Seminar – March 2011

18. Fault tolerant used for multiple goals • Improve robustness • Saving power consumption • Keep low area overhead • Reduce aging impacts • On going work • Improve multiple-fault tolerance capability • Compute online fault tolerance capability • Compute manufacturing yield Conclusion South European Test Seminar – March 2011