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This summary delves into the ISR process and corresponding CSL programming interface for CPINTC, elaborating on concepts such as interrupts, mapping, and configurations. Key topics include INTC, CPINTC functions, events handling, and interrupt generation. Useful for developers working with multi-core architectures like KEYSTONE, specifically focusing on the C6678 as an example.
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中断服务流程(ISR)与对应CSL编程接口之 CPINTC总结 Bruce Chen 2012-2-3
应用背景 • 基于KEYSTONE 多核架构 • 以C6678 为例
ISR 中断 CPINTC INTC 调用中断 处理函数 CPINTC: Chip-level interrupt controller. It aggregates interrupts. Mapping system interrupts to host interrupts. At most 1024 system interrupts can be handled while make at most 256 output . INTC: interrupt controller (inside corepac). Mapping 128 interrupts to 12 vectors, exception, NMI, reset.
CPINTC • 2 mappings; one is fixed while the other is programmable • channel num = host interrupt num System interrupts Host interrupts Channels Program mable fixed
What inside CPINTC • Take c6678 CPINTC for example CPINTC INTC0 Core0~3 INTC0 does services for core 0~3 INTC1 Core 4~7 INTC2 TPCC1 TPCC2 INTC3 Hyperlink TPCC0
CSL API • INTC configure • 1. INTC initial • CSL_intcInit • CSL_intcGlobalNmiEnable • CSL_intcGlobalEnable • 2.INTC mapping &hook callback function • CSL_intcOpen // map Event ID to Vector ID • CSL_intcPlugEventHandler // hook callback function
3. enable events • CSL_intcHwControl • CPINTC • 4. CSL_CPINTC_open //Open the handle to the CPINT Instance • CSL_CPINTC_disableAllHostInterrupt • CSL_CPINTC_mapSystemIntrToChannel • CSL_CPINTC_enableSysInterrupt • CSL_CPINTC_enableHostInterrupt • CSL_CPINTC_enableAllHostInterrupt
5. generate interrupt • ((CSL_CPINTC_RegsOvly)CSL_CP_INTC_0_REGS)->STATUS_SET_INDEX_REG //configure register
Reference • TMS 320C6678 datasheet • TMS320C66x DSP CorePac User Guide • KeyStone Architecture Interrupt Controller (INTC) User Guide
Reference code • pdk_C6678_1_0_0_11\packages\ti\csl\example\cpintc