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HVPS Configurations

HVPS Configurations. JEM EUSO Balloon Pierre Prat 17/09/2012. HVPS I/F configuration versions. Version 1: page 3 (C-W gain commands provided by PDM_Board) HVPS-1: HK SPI I/F + LVDS PDM_Board I/F + 28V 3.3V DC/ DC CV HVPS-2: 9 C-W

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HVPS Configurations

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  1. HVPS Configurations JEM EUSO Balloon Pierre Prat 17/09/2012

  2. HVPS I/F configuration versions • Version 1: page 3 (C-W gain commands provided by PDM_Board) • HVPS-1: HK SPI I/F + LVDS PDM_Board I/F + 28V 3.3V DC/DC CV • HVPS-2: 9 C-W • Version 2: page 4 (C-W gain commands provided by PDM_Board) • HVPS-1: 3 C-W + HK SPI I/F + LVDS PDM_Board I/F + 28V 3.3V DC/DC CV • HVPS-2: 6 C-W • Version 3 : page 5 (Internal C-W gain commands by D12 current measurement) • HVPS-1: 3 C-W + HK SPI I/F + 28V 3.3V DC/DC CV + FPGA/comparators/3 D12 current measurements • HVPS-2: 6 C-W + 6 D12 current measurements • Version 4 : page 6 (Internal C-W gain commands by D12 current measurement) • HVPS-1: 3 C-W + 28V 3.3V DC/DC CV + FPGA/comparators/3 D12 current measurements • HVPS-2: 6 C-W + 6 D12 current measurements • HVPS-3: HK SPI I/F

  3. HVPS-1 - HVPS-2 - HK - PDM-Board Interface Synoptic : version 1 28V (S) HVPS-2 HVPS-1 BAT_RET (P) GND_28V (S) D-Sub 9M D-Sub 9 F 28V_BAT (P) 3.3V (S) GND_3.3V (S) 9 C-W CS_DAC 9 analog signals 9 DAC 0-2.44V MOSI SCK D-Sub 37 F D-Sub 37 M D-Sub 37 F D-Sub 37 M CS_IO 9 bidirectional signals ON/OFF I/O expanders MOSI MISO 9 status signals STATUS SCK Interrupt D-Sub 9M D-Sub 9 F CN2 2 2 2 2 2 2 2 2 2 2 Interrupt MOSI MISO SCK CN3 CN4 CN9 4 differential receivers Micro-D 9 F D-Sub 15 F 4 differential receivers GND_M D-Sub 15 M Micro-D 9 M BATTERY 4 differential signals (LVDS) between PDM Board and HVPS-1 x 2 = 8 wires 6 Differential signals (LVDS) ( x2 = 18 wires)between HK and HVPS1 Micro-D 9 M D-Sub 15 M D-Sub 15 F Micro-D 9 F HK 4 differential transmitters PDM Board 4 differential transmitters 16 wires GND_M 2 differential receivers HVPS1 would have the DC/DC converters to isolate the powers needed by HVPS2 which would welcome the CW and switch system

  4. HVPS-1 - HVPS-2 - HK - PDM-Board Interface Synoptic : version 2 28V (S) HVPS-2 BAT_RET (P) 1 GND_28V (S) D-Sub 9 F D-Sub 9M 3.3V (S) 28V_BAT (P) 2 GND_3.3V (S) 6 C-W 3 C-W 3 ON/OFF 3 0-2.44V 6 x 14 HV lines 3 STATUS 3 x 14 HV lines CN9 CN3 CN2 CN4 D-Sub 37 F D-Sub 37 M D-Sub 37 M D-Sub 37 F HVPS-1 6 analog signals CS_DAC 9 MOSI 0-2.44V 9 DAC SCK 6 bidirectional signals CS_IO 9 ON/OFF I/O expanders MOSI 6 status signals MISO 9 D-Sub 9M SCK STATUS D-Sub 9 F Interrupt CN2 2 2 2 2 2 2 2 2 2 2 MOSI MISO SCK Interrupt CN3 CN4 GND_M 4 differential receivers CN9 Micro-D 9 F D-Sub 15 F 4 differential receivers GND_M D-Sub 15 M Micro-D 9 M BATTERY 4 differential signals (LVDS) between PDM Board and HVPS-1 x 2 = 8 wires 6 Differential signals (LVDS) ( x2 = 18 wires)between HK and HVPS1 D-Sub 15 M Micro-D 9 M D-Sub 15 F Micro-D 9 F HK 4 differential transmitters PDM Board 4 differential transmitters GND_M 16 wires 2 differential receivers HVPS1 would have the DC/DC converters to isolate the powers needed by HVPS2 which would welcome 6 C-W and switch system

  5. HVPS-1 - HVPS-2 - HK Interface Synoptic : version 3 28V (S) HVPS-2 BAT_RET (P) 1 GND_28V (S) D-Sub 9 F D-Sub 9M 3.3V (S) 28V_BAT (P) 2 GND_3.3V (S) 3 C-W 3 0-2.44V 3 ON/OFF D-Sub 37 F D-Sub 37 M D-Sub 37 M D-Sub 37 F 3 STATUS 6 C-W 3 x 14 HV lines CN9 CN3 CN4 CN2 6 I-D12 analog signals 3 I-D12 analog signals 6 x 14 HV lines 3 x 3 Comparators +FPGA CN2 CN3 CN4 CN9 CS_IO 4 CN status MISO 6 status signals 9 I/O expanders D-Sub 9M STATUS Interrupt D-Sub 9 F MOSI 9 6 bidirectional signals 2 2 2 2 2 2 SCK ON/OFF CS_DAC 6 analog signals 9 GND_M 9 DAC 0-2.44V MOSI SCK GND_M MOSI SCK Interrupt MISO BATTERY HVPS-1 4 differential receivers D-Sub 15 F 6 Differential signals (LVDS) ( x2 = 18 wires)between HK and HVPS1 D-Sub 15 M D-Sub 15 M GND_M HVPS1 would have the DC/DC converters to isolate the powers needed by HVPS2 which would welcome 6 C-W and switch system D-Sub 15 F HK 4 differential transmitters 2 differential receivers

  6. HVPS-1 - HVPS-2 – HVPS-3 - HK Interface Synoptic : version 4 28V (S) BAT_RET (P) HVPS-2 GND_28V (S) 1 D-Sub 9 F D-Sub 9M 3.3V (S) 28V_BAT (P) 2 GND_3.3V (S) 3 C-W 3 0-2.44V 3 ON/OFF D-Sub 15 F D-Sub 15 M D-Sub 15 M D-Sub 15 F 3 STATUS 3 x 14 HV lines 6 C-W CN9 CN3 CN4 CN2 6 I-D12 analog signals 3 I-D12 analog signals Comparators +FPGA CN2 CN3 6 x 14 HV lines HVPS-1 CN4 CN9 D-Sub 15 F D-Sub 15 M 3 x 3 GND_3.3V (S) 3.3V (S) 4 CN status D-Sub 15 M D-Sub 15 F D-Sub 9M 6 status signals D-Sub 9 F 9 STATUS MISO 2 2 2 2 2 2 I/O expanders Interrupt 6 bidirectional signals 9 MOSI ON/OFF D-Sub 25 F D-Sub 25 M D-Sub 25 F D-Sub 25 F GND_M SCK CS_DAC 6 analog signals 9 MOSI 0-2.44V 9 DAC GND_M BATTERY SCK CS_IO MOSI SCK Interrupt MISO HVPS-3 4 differential receivers 6 Differential signals (LVDS) ( x2 = 18 wires)between HK and HVPS1 D-Sub 15 F D-Sub 15 M GND_M HVPS1 would have the DC/DC converters to isolate the powers needed by HVPS2 which would welcome 6 C-W and switch system D-Sub 15 M D-Sub 15 F 4 differential transmitters HK 2 differential receivers

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