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Presenter ：梁正勳 Number:97662003

Phase-Adjustable Pipelining ROM-Less Direct Digital Frequency Synthesizer With a 41.66-MHz Output Frequency. Presenter ：梁正勳 Number:97662003. Outline. INTRODUCTION HIGH-SPEED ROM-LESS DDFS IMPLEMENTATION AND PHYSICAL MEASUREMENT CONCLUSION REFERENCES. INTRODUCTION.

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Presenter ：梁正勳 Number:97662003

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  1. Phase-Adjustable Pipelining ROM-Less Direct Digital Frequency Synthesizer With a 41.66-MHz Output Frequency Presenter：梁正勳 Number:97662003

  2. Outline • INTRODUCTION • HIGH-SPEED ROM-LESS DDFS • IMPLEMENTATION AND PHYSICAL MEASUREMENT • CONCLUSION • REFERENCES

  3. INTRODUCTION • DDFSs are very much preferred in some modern communication systems. • The bottleneck of the DDFS method is the generation of a pure sinusoidal output. • All of the ROM-based solutions suffer from ROM’s intrinsic drawbacks, namely low speed, large area, and high power consumption. • In this brief,we propose a novel pipelining ROM-less design for DDFSs that utilizes a trigonometric quadruple angle formula to attain a smaller error range. • The pipelining methodology and tunable phase selections are adopted to enhance the processing speed as well as the throughput.

  4. HIGH-SPEED ROM-LESS DDFS • A. Trigonometric First-Order Quadruple Angle Approximation The quadruple angle formula can be rearranged as follows: Hence, we redefine our first-order approximation method, which is called TA1(x) as follows:

  5. Second-Order Approximation

  6. System Design by Ten-Stage Pipelining Fig. 5 is a typical implementation of DDFSs in prior works. The slow and large ROM not only occupies a significant portion of the chip (or board) area but also degrades the operation frequency.

  7. System Design by Ten-Stage Pipelining The detailed block diagram of the proposed DDFS is shown in Fig. 6.

  8. System Design by Ten-Stage Pipelining • Phase Adjustment: • Phase Accumulation: • TA1(x) Approximation: • TA2(2) Approximation: Fig. 7. Signal flow of the proposed ROM-less DDFS.

  9. Pipelining • Phase Adjustment: • Phase Accumulation: if the “phase_adjust” command is enabled, “phase_interval” equals “phase_acc” plus “adjust_displace”. The mapping from the output phase angle of the proposed DDFS “θ” to “phase_value” and “x” is shown in Fig. 9.

  10. Pipelining • TA1(x) Approximation: Both the phase square and phase biquadratic calculation are realized by the mentioned squarer decomposition. • TA2(2) Approximation: Fig. 10 The output of “stage8” is cos_out as shown in Fig. 10. “stage9” implements the amplitude complement of “stage8”. The mapping of “phase_value” and “cos_out” is shown in Fig. 11. Fig. 11

  11. IMPLEMENTATION AND PHYSICAL MEASUREMENT Fig. 12 shows the transition from a 5.55-MHz sine output to a 41.66-MHz O/P given the worst condition.

  12. IMPLEMENTATION AND PHYSICAL MEASUREMENT Table I summarizes the performance of our work and prior methods. Fig. 14 is the die photo of the proposed design. Table II summarizes the characteristics of the chip.

  13. IMPLEMENTATION AND PHYSICAL MEASUREMENT Fig. 16 shows the waveform of the synthesized cosine wave derived from the measured samples.

  14. CONCLUSION • In this brief, we have presented a novel implementation utilizing pipelining to carry out a ROM-less DDFS, which is based on the quadruple angle equality equation. • Not only are the spurious tones reduced, but the second-order error correction has also been simulated to justify the capability of subsiding the noise power of the harmonics. • The proposed design is fully proven on silicon to reveal its feasibility.

  15. REFERENCES [1] G. W. Kent and N.-H. Sheng, “A high purity, high speed direct digital synthesizer,” in Proc. 49th IEEE Int. Frequency Control Symp., 1995, pp. 207–211. [2] V. F. Kroupa, Direct Digital Frequency Synthesizers. Piscataway, NJ: IEEE Press,1998. [3] G. Van Andrews et al., “Recent progress in wideband monolithic direct digital synthesizers,” in Proc. IEEE MTT-S Inter. Microw. Symp. Dig.,1996, vol.3, pp.1347–1350. [4] M. J. Flanagan and G. A. Zimmerman, “Spur-reduced digital sinusoid synthesis, ” IEEE Trans. Commun., vol. 43, no. 7, pp. 2254–2262, Jul.1995. [5] V. F. Kroupa, V. Cizek, J. Stursa, and H. Svandova, “Spurious signals in direct digital frequency synthesizers due to the phase truncation,” IEEE Trans. Ultrason., Ferroelectr., Freq. Control, vol. 47, no. 5, pp. 1166–1172, Sep. 2000. [6] R. Larson and S.-L. Lu, “Interpolation-based digital quadrature frequency synthesizer,” in Proc. 13th Annu. IEEE Int. ASIC/SOC Conf., 2000, pp. 48–52.

  16. The End Thank you for your attentions !

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