Shahana Pagen

1. Briefing: RT54SX-S, RTSX-SU, RTAX-S, and Eclipse FPGAs for Spaceborne ApplicationActel SX-S and AX Signal and Power Integrity Considerations Shahana Pagen

2. Actel SX-S and AX Signal and Power Integrity Considerations • Actel datasheets specify a 500mV undershoot limit • Datasheet also specifies a +/-10% tolerance on voltage supplies: • 3.3V ranging from 3.0 to 3.6 • 2.5V from 2.25 to 2.75 • 1.5V from 1.35 to 1.65 • In order to design PWB’s to meet Actel requirements, these limits must be carefully analyzed to guarantee that the parts will not be stressed over temperature and voltage extremes • Critical signals need to be analyzed to detect potential undershoot, overshoot, ringing, crosstalk problems • Decoupling strategies must be evaluated and analyzed to ensure stable voltages during operation, high frequency switching • Guarantee performance by design, not test

3. SX-S and AX Simulation Cases • The following critical interfaces have been analyzed and simulated: • Single driver/receiver scenarios to evaluate the various IO drive characteristics • 4 load bi-directional data bus with Actel SX-SU drivers and receivers • PCI backplane with Actel target devices to determine optimal termination to meet Actel undershoot requirements • Actel SX-S package characteristics, decoupling and SSO performance • Actel AX package characteristics, decoupling and SSO performance

4. SX-S IO Characteristics Summary • SX-S IO driver can be either high slew or low slew, however: • Low slew only effects the falling edge • Rising edge rate is not any slower • No selectable output drive options, only one drive strength available • Without termination signals are never seen to remain within the 500mV maximum undershoot requirement (undershoot reaching ~700mV), making terminating every output necessary even if design uses slow slew output driver • With termination undershoot is ~350 mV (in spec) Yellow: LVTTL LS, no termination Green: LVTTL HS, no termination Red: LVTTL LS, 56 Ohm termination Blue: LVTTL HS 56 Ohm termination

5. SX-S Comparison Measurements • Measurement made on Development Unit which had 33 Ohm termination resistors • Fall Time: 1.1 ns • Undershoot: ~600 mV Simulated Measurements

6. SX-S Comparison Measurements • Simulated rise and fall times using Actel models are typically somewhat faster compared to real-world measurements, however, the differential is small enough that simulation gives a very good estimation of worse case behavior • Fall Time: 1.6 ns • Undershoot: ~500 mV Actual Measurements

7. AX IO Characteristics Summary • AX IO driver can be either high slew or low slew, with slow slew effecting both edges of the signal • 4 output drive options available: 8, 12, 16, 24 mA • The AX slow slew option eliminates undershoot problems even without termination: recommended option where design timing can be met with slow slew driver • Designers can get some advantage using a lower drive output, with the high slew option, though may not be enough to completely eliminate the need for termination • Termination may still be required with high slew drive 700 mV 800 mV 250 mV 500 mV 50 mV Red: LVTTL HS, 24 mA, no termination Orange: LVTTL HS, 4 mA, no termination Blue: LVTTL LS, 4 mA, no termination Magenta: LVTTL HS, 24 mA,56 Ohm termination Green: LVTTL HS, 4 mA,56 Ohm termination

8. SX-S Multi Drop Data Bus Simulation Summary • Data bus with 4 bi-directional loads simulated • Different routing topologies compared – star, min-span • Different termination schemes compared – source series, destination RC, terminating at one point or multiple points • Worst case drivers used – Actel RTSX-S with fast slew, high output drive • Star topology seen to have marginal performance improvement over min-span, but not sufficient to replace need for termination, also takes up additional routing resources • Source series termination at each driver seen to have best performance • Similar finding to single source/destination case 350 mV 800 mV Blue: RC termination at each receiver Magenta: Series termination at each driver Green: No termination

9. PCI Data Bus Simulation Summary • 8 Slot PCI bus with 6 target cards simulated • 2-6 load cases simulated • PCI CLK speed 33 MHz, with effective data bus switching rate 16.5MHz • External diode seen to eliminate undershoot, even with the minimum of 2 loads, however that necessitates additional components on the backplane • 25 Ohm termination at the target cards (keeping SBC termination at 10 Ohms) reduces undershoot, allows 33 MHz operation when 6 loads are used in the system and provides best results 60 mV 500 mV 760 mV Red: Original PCI 10 Ohm stub termination Green: PCI 10 Ohm, with backplane diode termination Blue: PCI stub termination of 25 Ohm with no diode

10. PCI Data Bus Comparison Measurements • Lab measurement shows close correlation to the simulated results • In populated chassis, measurement cannot be taken at Actel device pin, so for comparisons simulated waveform and lab measurement taken at J1 connector pin • Comparison with 10 Ohm stub resistor only. 810 mV 700 mV Simulated Actual

11. PCI Data Bus Comparison Measurements • Comparison with 10 Ohm stub and diode on the backplane 580 mV 560 mV Simulated Actual

12. SX-S Package Characteristics Summary • RTSX-S package has poor distribution of power/supply pins around the package • In the diagram shown (CQ256): • GND: GREY, QTY 19 • Core Supply: Red, QTY 9 • IO Supply: Magenta, QTY 12 • User IO: Green, QTY 201 • Inadequate power and ground pins, distributed unevenly around the package. Difficult to define design pin-out without violating SSO constraints • In addition, all package ground pins are not internally connected to the same plane, instead there are 3 “types” of grounds within the package (GNDQ, GNDI, and GNDA) • GNDQ is not directly connected to GNDI or GNDA but has a PN junction to these grounds. • GNDI and GNDA are not directly connected internally but have 2 ohms between them. • GNDI pins are connected together via some kind of low resistance circuit on the ceramic substrate. • GNDA pins are connected together via some kind of low resistance circuit on the ceramic substrate. • This effects the IO current return paths and decoupling effectiveness

13. SX-S Package Simulation Summary • Simulations performed to plot input impedance curve across range of frequencies with and without decoupling capacitors • Assuming .5A current draw and 10% ripple on supply, target impedance: • 2.5V * 10/100/.5 = . 5 Ω • 3.3 * 10/100/.5 = .66 Ω • Assuming 1.7 ns rise/fall time, signal bandwidth = .35/Trise = 205 MHz • SX-S poor package characteristics make it difficult to meet low impedance power delivery even with decoupling capacitors • Careful study must be done to select capacitors with lowest ESR and ESL at required frequency CORE SUPPLY .6 Ohm Red: No Decoupling Capacitors Green: Decoupling Capacitors IO SUPPLY .6 Ohm

14. SX-S SSO Simulation Summary • Simulations performed to plot IO voltage during a 32-bit bus switching cycle. • Simulations show that worse case bus switching could push voltage outside of 10% tolerance range SX-S Core Supply 2.29V 2.75V 2.25V Simulated Actual

15. SX-S SSO Simulation Summary • This agrees to assessment based on input impedance analysis • Though real-world is typically somewhat better than simulation predicts, few things to consider: • Difficult to take high fidelity measurements right on the Actel supply pin • Even at room temp, best case measurement shows voltages remaining barely within spec SX-S IO Supply 3.6V 3.09V 3.0V Actual Simulated

16. AX Package Characteristics Summary • RTAXS package has superior distribution of power/supply pins around the package • In the diagram shown (CQ352): • GND: GREY, QTY 56 • Core Supply: Red, QTY 44 • IO Supply: Magenta, QTY 29 • User IO: Green, QTY 179 • Symmetrically distributed power and ground pins around the package, proportional to available IO pins. Far easier to define design pin-out without violating SSO constraints

17. AX Package Simulation Summary • RTAXS package has superior distribution of power/supply pins around the package • Simulations performed to plot input impedance curve across range of frequencies with and without decoupling capacitors for both IO and core voltage • Assuming .5A current draw and 10% ripple on supply, target impedance: • 1.5V * 10/100/.5 = .3 Ω • 3.3 * 10/100/.5 = .66 Ω • Assuming 1.7 ns rise/fall time, signal bandwidth = .35/Trise = 205 MHz • AX impedance response is much better, and given careful part selection and routing, it is possible to meet target impedance requirements CORE SUPPLY .2 Ohm IO SUPPLY Red: No Decoupling Capacitors Green: Decoupling Capacitors .1 Ohm

18. AX SSO Simulation Summary • Simulations performed to plot IO voltage during a 32-bit bus switching from all zeros to all Fs. • Worse case bus switching still maintains voltages within 10% tolerance range • If real-world proves to be better than simulation (similar to SX-S package), that will increase design margin 3.6V 1.65V 1.35V 3.0V

19. Closing Thoughts • Actel SX-S and AX device family IO and package characteristics no longer allow for “rule of thumb” design methodology. • Fast edge rates, board switching frequencies, necessitate careful analysis and PWB simulation to guarantee board performance. • Actel has made many improvements with the AX family, as seen through analysis: however RTAX part has not been available yet to perform correlation measurements, thus all conclusions currently are drawn from simulated results. It is expected however, that as with the SX-S family, strong correlation will be found with simulations providing the worst case circuit analysis. • Board designers must analyze their circuit design and allocate routing resources necessary to optimally place and route termination components, decoupling capacitors. This may take a fair amount of routing space, which if not planned for from the beginning, may not be easy to accomplish midstream in a PWB layout phase, and impossible to accomplish after hardware is fabricated.