1 / 44

Embedded Systems: Hardware Components (part II)

Embedded Systems: Hardware Components (part II). Ed F. Deprettere Leiden Embedded Research Center, Leiden Institute of Advanced Computer Science Leiden University, The Netherlands. Outline. Generic Embedded System component structure Sensors Analog-to-Digital (A/D-) converters

heidi
Download Presentation

Embedded Systems: Hardware Components (part II)

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Embedded Systems: Hardware Components (part II) Ed F. Deprettere Leiden Embedded Research Center, Leiden Institute of Advanced Computer ScienceLeiden University, The Netherlands

  2. Outline • Generic Embedded System component structure • Sensors • Analog-to-Digital (A/D-) converters • Computation Components • General Purpose Processors (GPPS) • Application Specific Instruction Set Processors (ASIPs) • Reconfigurable Processing Units (RPUs) • Application Specific Integrated Circuits (ASICs) • Memory • Input/Output Devices • Communication Infrastructure • Digital-to-Analog (D/A) converters • Actuators Embedded Systems and Software by Todor Stefanov 2010

  3. Embedded Systems Hardware Embedded Systems hardware is frequently used in a loop(“hardware in a loop“): Embedded System Display InformationProcessing A/D-converters sample-and-hold D/A converters Environment Actuators Sensors rain light Embedded Systems and Software by Todor Stefanov 2010

  4. Information Processing System:Input/Output Devices Memory Cache Memory Memory ScratchPad ASIC ASIPMicroCtrl DSP VLIW RPU FPGA GPP … CommunicationInfrastructure I/O device I/O device Memory Memory … … Embedded Systems and Software by Todor Stefanov 2010

  5. Examples of I/O Devices • Timers • WatchDogs • Pulse Width Modulators (PWM) • Universal Asynchronous Receiver Transmitter (UART) • Inter Integrated Circuit (I2C) • … Philips 83C552: 8 bit-8051 based microcontroller Embedded Systems and Software by Todor Stefanov 2010

  6. How Computation Components “talk” to I/O Devices? I/O Devices are mapped in the address space of Computation Components (CC), i.e., CCs communicate with I/O devices simply by reading/writing from/to memory cells. • Two general methods for access • Polling - Includes, a kind of busy-waitloop • Interrupts - Using interrupt line of CC to provide service to devices Local Mem Memory Map 0 I/O device 1 2 3 I/O device 2 5 GPP ASIP RPU I/O Device 1 : 50 Mem 1 100 BUS : 200 I/O Device N Mem1 Local Mem N Embedded Systems and Software by Todor Stefanov 2010

  7. Polling: Busy-Wait Interface SLAVE MASTER Status Regs mechanism GPP ASIP RPU data/address Control Regs Issues: • MASTER is tied up in communication with device until I/O operation is done • No other work can be accomplished by MASTER • Typically one MASTER in system, but many I/O devices • Only really useful if devices are fast • No time consuming context switches Data Regs • Continuous polling Loop (until device ready) Check device End-loop • Periodicpolling Embedded Systems and Software by Todor Stefanov 2010

  8. Interrupt Interface SLAVE MASTER intr request Status Regs mechanism GPP ASIP RPU data/address Control Regs • When I/O device needs MASTER attention, an interrupt signal is sent • MASTER is “forced” to suspend its current task • Interrupts can be ignored (masked) when critical task is executed • MASTER acknowledges interrupt and jumps to interrupt service routine • When finished control is returned to the interrupted task intr ack Data Regs • Key observations: • MASTER is free to do something else until attention is needed • Improves utilization of MASTER, leading to a much better response • I/Os can proceed asynchronously • Time consuming context switches Embedded Systems and Software by Todor Stefanov 2010

  9. Communication with many I/Os interrupt acknowledge device 1 device 2 device n • Interrupt Identification • SW polling (check status registers) • HW polling (ACK signal propagated in Daisy Chain) • Interrupt Priority (in case multiple interrupts to be served) interrupt requests GPP ASIP RPU L1 L2 .. Ln Embedded Systems and Software by Todor Stefanov 2010

  10. Memory Cache Memory Memory ScratchPad ASIC ASIPMicroCtrl DSP VLIW RPU FPGA GPP … I/O device I/O device Memory Memory … … Information Processing System:Communication Infrastructure CommunicationInfrastructure Embedded Systems and Software by Todor Stefanov 2010

  11. Types and Requirements • Types of Communication Infrastructure • Single Bus • Single shared resource, thus may become the bottleneck in the system • Multiple Busses/Crossbar Switches • Wire Switching communication infrastructure • Networks (on Chip) • Packet Switching communication infrastructure • Requirements for Embedded Systems • Performance • bandwidth and latency • guaranteed behavior (real-time) • Efficiency • cost (material, installation, maintenance) • low power • Robustness • fault tolerance • maintainability, diagnoseability • security, safety Embedded Systems and Software by Todor Stefanov 2010

  12. Generic Bus Structure m • What is a BUS? • Set of wires • Common protocol for communication with devices • Address wires: Data wires: Control wires: n c Embedded Systems and Software by Todor Stefanov 2010

  13. Generic Fixed-delay Access Protocol read = 1 addrs = A R/W W R/W data mem[adrs] = data R addrs data = mem[adrs] reg = data SLAVE device MASTER Embedded Systems and Software by Todor Stefanov 2010

  14. Generic Variable-delay Access Protocol read = 1 adrs = A R/W done = 0 mem[adrs] = data done = 1 data W R/W R n adrs done data = mem[adrs] done = 1 y done SLAVE device reg = data MASTER Embedded Systems and Software by Todor Stefanov 2010

  15. Typical Bus Access Protocol clock R/W’ Address enable adrs Data Ready’ data write read time Embedded Systems and Software by Todor Stefanov 2010

  16. Memory Memory Memory ASIC ASIP RPU GPP BUS I/O device I/O device Memory Memory … … What if Multiple Masters “want” the BUS simultaneously • Arbiter is used • Controls access to the shared bus • Uses arbitration policy to select master to grant access to bus • Arbitration policy • Centralized Arbitration • Round Robin policy • Priority policy • TDMA policy • Distributed Arbitration • Carrier Sense Multiple Access / Collision Detection (CSMA/CD) Embedded Systems and Software by Todor Stefanov 2010

  17. Memory Memory Memory ASIC ASIP RPU GPP … I/O device Memory I/O device Memory … … Centralized Arbitration • Two important control signals per MASTER, i.e., • bus_request – from MASTER to ARBITER • bus_granted – from ARBITER to MASTER • Minimal change is required if new components are added to the system Arbiter BUS Embedded Systems and Software by Todor Stefanov 2010

  18. Arbitration Policies (1) • Random • Randomly select master to grant bus access to • Static priority • Masters assigned static priorities • Higher priority master request always serviced first • Can be pre-emptive or non-preemptive • May lead to starvation of low priority masters • Round Robin (RR) • Masters allowed to access bus in a round-robin manner • No starvation – every master guaranteed bus access • Inefficient if masters have vastly different data injection rates • High latency for critical data stream Embedded Systems and Software by Todor Stefanov 2010

  19. Arbitration Policies (2) • Time Division Multiple Access (TDMA) • Assign slots to masters based on bandwidth requirements • If a master does not have anything to read/write during its time slots, leads to low bus utilization • Choice of time slot length and number critical • Predictable behavior suitable for real-time Embedded Systems • TDMA/RR • Two-level scheme • If master does not need to utilize its time slot, second level RR scheme grants access to another waiting master • Better bus utilization • Higher implementation cost for scheme (more logic, area) Embedded Systems and Software by Todor Stefanov 2010

  20. Arbitration Policies (3) • Dynamic priority • Dynamically vary priority of master during application execution • Gives masters with higher injection rates a higher priority • Requires additional logic to analyze traffic at runtime • Adapts to changing data traffic profiles • High implementation cost (several registers to track priorities and traffic profiles) • Programmable priority • Simpler variant of dynamic priority scheme • Programmable register in arbiter allows software to change priority Embedded Systems and Software by Todor Stefanov 2010

  21. Memory Memory Memory ASIC ASIP RPU GPP … Arbiter Arbiter Arbiter Arbiter BUS I/O device Memory I/O device Memory … … Distributed Arbitration • Requires fewer signals compared to the centralized approach • More hardware duplication, more logic/area, less scalable Embedded Systems and Software by Todor Stefanov 2010

  22. Distributed Arbitration Example: CSMA/CD • Carrier Sense Multiple Access / Collision Detection • Try to avoid and detect collisions: • before starting to transmit, MASTER checks whether the bus is idle • if a collision is detected (several MASTERS started almost simultaneously), wait for some time (back-off timer) • Repeated collisions result in increasing back-off times Embedded Systems and Software by Todor Stefanov 2010

  23. How to Connect Different Busses and Interfaces? memory memory memory • Use Bus Bridges • They act as slave on one side and master on the other ASIP RPU CPU BUS3 Bridge1 BUS2 BUS1 Bridge3 I/O device I/O device Bridge2 BUS4 memory memory … Embedded Systems and Software by Todor Stefanov 2010

  24. Multiple Busses • IBM Cell ring bus communication architecture Embedded Systems and Software by Todor Stefanov 2010

  25. Crossbar Switch • Full-crossbar/matrix busPoint-to-Point • Partial-crossbar/matrix bus Embedded Systems and Software by Todor Stefanov 2010

  26. Network-On-Chip: Introduction • Network-on-chip (NoC) is a packet switched on-chip communication network • NoCs use packets to route data from the source to the destination PE via a network fabric that consists of • network interfaces (NI) • switches (routers) • interconnection links (wires) Embedded Systems and Software by Todor Stefanov 2010

  27. Network-On-Chip: Introduction • NoCs are an attempt to scale down the concepts of large-scale networks, and apply them to the Embedded System-on-chip (SoC) domain • NoC Properties • Reliable and predictable electrical and physical properties • Regular geometry that is scalable • Flexible QoS guarantees • Higher bandwidth • Reusable components • Buffers, arbiters, routers, protocol stack Embedded Systems and Software by Todor Stefanov 2010

  28. Network-On-Chip: Topology 1-D Torus 2-D Torus 2-D Mesh Fat Tree Octagon Butterfly Irregular or Ad-hoc Embedded Systems and Software by Todor Stefanov 2010

  29. Network-On-Chip: Issues • Very hot research topic at the moment • NO wide adoption in Industry because • Power • complex NI and switching/routing logic blocks are power hungry • several times greater than for current bus-based approaches • Latency • additional delay to packetize/de-packetize data at NIs • flow/congestion control and fault tolerance protocol overheads • delays at the numerous switching stages encountered by packets • even circuit switching at routers has overhead • lags behind what can be achieved with bus-based/dedicated wiring • Lack of tools and benchmarks Embedded Systems and Software by Todor Stefanov 2010

  30. All this could be on a single chip!!!System-on-chip (SoC) Memory Cache Memory Memory ScratchPad ASIC ASIPMicroCtrl DSP VLIW RPU FPGA GPP … CommunicationInfrastructure I/O device I/O device Memory Memory … … Embedded Systems and Software by Todor Stefanov 2010

  31. SDRAM Serial I/O video-in video-out PCI bridge I2C I/O timers audio-out I$ VLIW cpu audio-in D$ Example of SoC Philips Trimedia Chip Off-chip memory peripherals Programmable core High-way bus Embedded Systems and Software by Todor Stefanov 2010

  32. Examples of Configurable SoC Embedded Systems and Software by Todor Stefanov 2010

  33. Trend: Multi-Processor SoC (MPSoC) http://www.mpsoc-forum.org/2007/slides/Hattori.pdf Embedded Systems and Software by Todor Stefanov 2010

  34. Multi-Processor System-on-Chip (1) http://www.mpsoc-forum.org/2007/slides/Hattori.pdf Embedded Systems and Software by Todor Stefanov 2010

  35. Multi-Processor System-on-Chip (2) http://www.mpsoc-forum.org/2007/slides/Hattori.pdf Embedded Systems and Software by Todor Stefanov 2010

  36. Multi-Processor System-on-Chip (3) http://www.mpsoc-forum.org/2007/slides/Hattori.pdf Embedded Systems and Software by Todor Stefanov 2010

  37. Another Example of MPSoC Embedded Systems and Software by Todor Stefanov 2010

  38. Embedded Systems Hardware Embedded Systems hardware is frequently used in a loop(“hardware in a loop“): Embedded System Display InformationProcessing A/D-converters sample-and-hold D/A converters Environment Actuators Sensors rain light Embedded Systems and Software by Todor Stefanov 2010

  39. Digital-to-Analog (D/A)-converters Various types, can be quite simple, e.g.: Embedded Systems and Software by Todor Stefanov 2010

  40. Ii Output voltage ~no. represented by x ° * Due to Kirchhoff’s laws :  Loop rule*: I ~ nat (x), wherenat(x): natural number represented byx; Junction rule°: Hence: Finally: Op-amp turns current I ~ nat (x) into a voltage ~ nat (x) Embedded Systems and Software by Todor Stefanov 2010

  41. Reconstruction Analog from Digital? Filter(Inter-polation) S/H A/D-converter D/A-converter • According to Nyquist theorem: • Analog input to sample-and-hold can be precisely reconstructed from its output if • sampling frequency double the highest input frequency in input voltage • Digitizing values in the A/D generates additional uncertainty preventing precise reconstruction of initial values. Can be modeled as additional noise • Infinite bits for quantization would remove noise Embedded Systems and Software by Todor Stefanov 2010

  42. Embedded Systems Hardware Embedded Systems hardware is frequently used in a loop(“hardware in a loop“): Embedded System Display InformationProcessing A/D-converters sample-and-hold D/A converters Environment Actuators Sensors rain light Embedded Systems and Software by Todor Stefanov 2010

  43. Actuators • Convert a command to a physical stimulus (e.g., heat, light, sound, pressure, magnetism, or other mechanical motion) • May require analog interface • Output physical stimulus varies in range and modality • Large (industrial) control actuators • Pneumatic systems: physical motion • Optical output • IR, LEDs, displays, etc. • Motor controllers • DC, stepper, servo, … • Sound • Loudspeakers, etc. • … Embedded Systems and Software by Todor Stefanov 2010

  44. Stepper Motor • Stepper motor: rotates fixed number of degrees when given a “step” signal • In contrast, DC motor simply rotates when power applied, and coasts to stop • Rotation achieved by applying specific voltage sequence to coils • Controller greatly simplifies this • Stepper motors usedcommonly in hard drives • Head motor (stepper) • Spindle motor (DC) Embedded Systems and Software by Todor Stefanov 2010

More Related