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Package

Package. Basic functions in library. Library IEEE. Std_logic is gedefinieerd in het package: “ieee.std_logic_1164” Dit package zit in de library : “library IEEE” Oproepen van verschillende Packages uit library IEEE library ieee; use ieee.std_logic_1164. all ; (standaard data types)

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Package

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  1. Package Basic functions in library VHDL package

  2. Library IEEE • Std_logic is gedefinieerd in het package: • “ieee.std_logic_1164” • Dit package zit in de library : • “library IEEE” • Oproepen van verschillende Packages uit library IEEE • library ieee; • use ieee.std_logic_1164.all; (standaard data types) • use ieee.std_logic_arith.all; (rekenkundige bewerkingen) VHDL package

  3. Package declaration -- Package declaration package name_of_package is package declarations end package name_of_package; VHDL package

  4. Voorbeeld Package declaration library ieee; use ieee.std_logic_1164.all; package basic_func is -- AND2 declaration component AND2 port (in1, in2: in std_logic; out1: out std_logic); end component; -- OR2 declaration component OR2 port (in1, in2: in std_logic; out1: out std_logic); end component; end package basic_func; VHDL package

  5. Oproepen package Library ieee; use ieee.std_logic_1164.all; Library work; Use work.basic_func.all; • Work is de naam van het working library • Basic_func is het package in de library • .all wil zeggen dat we alles willen gebruiken uit dit package VHDL package

  6. Overzicht package files “oefening auto alarm” • .vhd file AND1 • .vhd file OR1 • .vhd file NOT1 • .vhd file test_package • Roept AND, OR, NOT op • Wordt bewaard in WORK library • .vhd file warning1_package • Roept package (test_package) op uit work library VHDL package

  7. voordeel • De package hoeft niet in de zelfde map te staan als het top design VHDL package

  8. Simpel voorbeeld LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY AND1 IS PORT( in1, in2 : IN STD_LOGIC; out1 : OUT STD_LOGIC); END AND1; ARCHITECTURE a OF AND1 IS BEGIN out1 <= in1 and in2 END a; VHDL package

  9. Voorbeeld met package • .vhd file AND poort LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY AND1 IS PORT( in1, in2 : IN STD_LOGIC; out1 : OUT STD_LOGIC); END AND1; ARCHITECTURE a OF AND1 IS BEGIN out1 <= in1 and in2 END a; VHDL package

  10. Voorbeeld met package • .vhd file package LIBRARY IEEE; USE IEEE.std_logic_1164.all; package test_package is component AND1 PORT( in1, in2 : IN STD_LOGIC; out1 : OUT STD_LOGIC); end component; end test_package; VHDL package

  11. Voorbeeld met package .vhd file top design LIBRARY IEEE; USE IEEE.std_logic_1164.all; Library work; use work.test_package.all; ENTITY warning1_package IS PORT( DOOR, IGNITION, SBELT : IN STD_LOGIC; WARNING1 : OUT STD_LOGIC); END warning1_package; ARCHITECTURE a OF warning1_package IS signal DOOR_NOT, SBELT_NOT, B1, B2: std_logic; BEGIN U2: AND1 port map (IGNITION, DOOR_NOT, B1); U3: AND1 port map (IGNITION, SBELT_NOT, B2); end a; VHDL package

  12. Oefening dobbelsteen • Zie site. VHDL package

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