1 / 12

Architecture Selection of a Flexible DSP Core Using Re-configurable System Software

Architecture Selection of a Flexible DSP Core Using Re-configurable System Software. July 18, 1998 Jong-Yeol Lee Department of Electrical Engineering, KAIST. Agenda. Introduction MetaCore C Compiler MetaCore Assembler MetaCore Instruction Set Simulator

heller
Download Presentation

Architecture Selection of a Flexible DSP Core Using Re-configurable System Software

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Architecture Selection of a Flexible DSP Core Using Re-configurable System Software July 18, 1998 Jong-Yeol Lee Department of Electrical Engineering, KAIST

  2. Agenda • Introduction • MetaCore C Compiler • MetaCore Assembler • MetaCore Instruction Set Simulator • “Compile-Simulate-Refine” Procedure of Architecture Selection • Experimental Results • Conclusion

  3. Introduction • Application-Specific Instruction set Processor(ASIP) • maximize the performance on a specific application • parameterized architecture • Major issues in ASIP design • performance & cost efficiency • instruction set & micro-architecture • diverse exploration of the design space • short design turnaround time • how efficiently transform the higher-level specification into lower-level implementation • application program development tools • compiler, assembler, ISS(Instruction Set Simulator) • Re-configurability

  4. Introduction • MetaCore is a flexible DSP core • MetaCore can be modified easily by just changing hardware parameters • MetaCore has special features for DSP applications(e.g. MAC unit and hardware loop unit) • To support the flexible core • The system software must be re-configurable • For re-configurability, each software has its own form of machine description • Using re-configurable system software • Many architectures can tested by iterating “compile-simulate-refine” cycles

  5. Parameter File B inst = 16bit general_ reg = 28 address_ reg = 8 minmaxALU = 1 Assembly Code B : min A0, R1 mvtom *AR2(0), A0 : Parameter File A inst = 16bit general_ reg = 28 address_ reg = 8 minmaxALU = 0 ... Assembly Code A : Amin : cmp A0, R1 b.lt LLmin cla A0 add A0, R1 LLmin : mvtom *AR2(0), A0 : Application C Program main() { ... m = min(m,t) ... } Machine Description MCC : . . . MetaCore C Compiler(MCC) • MetaCore C Compiler • Can be configured by changing parameters • Can be used to explore architectures Operation of MCC

  6. Assembly Language Definition // instruction : (operation field) (operand field) add : 80 (OP_ALU) sub : AF (OP_ALU) u_add : 8F (OP_ALU) Mapping Table Assembly Code ADD A1, R7 SUB A0, R1 U_ADD A0, A1 B LOOP Object Code 80 F0 AF 47 8F F1 31 41 Assembler MASM MetaCore Assembler(MASM) • User can define new instructions • Mapping table is automatically reconstructed from Assembly Language Definition Operation of MASM Format Converter

  7. U_ADD:B10001111,2,6 { Operands1 = GetSource 1; …. Result = AddOperands; SetConditionCodes; } Instruction Description Format Tree Builder Instruction Usage Statistics Decoding Tree Object Code 80 F0 AF 47 8F F1 31 41 Simulation Core Program Output MISS MetaCore Instruction Set Simulator(MISS) • MetaCore Instruction Set Simulator • Enables fast simulation on instruction level • Supports re-configurability using Instruction Description Format • Can be used as a debugger of assembly codes Operation of MISS

  8. Instruction-set Simulator Compiler Assembler Simulation Result Architecture Parameter Assembler Language Definition Instruction Description Format OK? No Architecture Refinement Yes Selected Architecture Architecture Selection Procedure • “Compile-simulate-refine” cycle Application C code

  9. Experimental Results • Performance impact of accumulators • The reference architecture has six address registers and ten general purpose registers

  10. Experimental Results • Parameter selection considering generated code size • If the code size should be smaller than 32K bytes, 16 general purpose register and 4 address registers will be enough

  11. 5% 20467 19923 2.7% 16 10% 20467 20019 2.2% 15 ADPCM 15% 20563 20115 2.2% 13 20% 20707 20259 2.2% 10 5% 20467 19971 2.5% 16 10% 20515 20067 2.2% 14 IDCT 15% 20563 20115 2.2% 13 20% 20659 20211 2.2% 11 5% 20419 19923 2.5% 17 10% 20419 19923 2.5% 17 Viterbi 15% 20467 19971 2.5% 16 20% 20467 19971 2.5% 16 Experimental Results • Find minimum area under speedup constraints • Use simple iterative heuristic Speedup constraint Obtained area Optimal area Area overhead Number of iterations Benchmark

  12. Conclusion • Present re-configurable system software for a flexible DSP core • Show that the re-configurable system software can be used to select the most suitable architecture for a given application • Code Optimization will be major future work

More Related