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SC2005 Transport Demultiplexer

SC2005 Transport Demultiplexer. Steve Horeff DTV Source Applications Broadband Entertainment Division July 2001. Agenda for Transport Demultiplexer. Features Demux Pipeline Stages Channel interface PID Processor DVB Descrambler Dispatcher A/V Interface PCR Recovery Auxiliary Port

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SC2005 Transport Demultiplexer

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  1. SC2005 Transport Demultiplexer Steve Horeff DTV Source Applications Broadband Entertainment Division July 2001

  2. Agenda for Transport Demultiplexer • Features • Demux Pipeline Stages • Channel interface • PID Processor • DVB Descrambler • Dispatcher • A/V Interface • PCR Recovery • Auxiliary Port • Host Interface

  3. Demux Features • MPEG-2 ISO/IEC 13818-1 transport stream compliant • 13.5 Mbytes/sec maximum input rate • Direct interface to LSI demod devices (724, 734, 768, 780) • 30 general-purpose PIDs, two dedicated for audio and video • DVB compliant descrambler • 33 Cyclic buffers for PSI, DPS, PRV and private PES • Error detection and handling (TEI, lost packet, discontinuity) • CRC checking for all section data • Aux I/O port

  4. Demux Block Diagram

  5. Channel Interface • Features • Serial or Parallel Input • Maximum data rate of 13.5 Mbytes/sec (parallel) • Sync Byte Detection and Synchronization • User Selectable Hysteresis on Lock/Unlock • 128-byte Channel FIFO • Interrupt signaling and Status flag handling • Clock Recovery Block • Transport packets error detection

  6. Demux Pipeline PID Filter Channel i/f Level 2 Filter Descrambler Transport packets Transport headers TS/PES payload Section Filter Dispatcher Level 3 Filter A/V Decoder A/V PES PES headers Cyclic Buffers PSI/PRV/private PES

  7. Packet Processing Flowchart

  8. PID Tables • 32 PID indexes • 30 General-Purpose PID Filters • One dedicated Audio PID • One dedicated Video PID • PID Value register • PID Control register • Activate, Packet type, Key index, etc. • Control bits for TS and PES header filters • Filter Enable register

  9. Transport Packet Types

  10. PID Preprocessor • PID Match Filtering • Compare starts at PID index 31 • ACT bit is checked • Parses the TS packet header and extracts descrambling information • Transport Header Filter (Level 2) • Splice Management • PID Monitoring

  11. Transport Header Filter - Level 2 • Works for all packet types • Enable/disable control in PID Control register • Four sets of 11-bit match/mask filters • transport_error_indicator 1 bit • payload_unit_start_indicator 1 bit • transport_priority 1 bit • transport_scrambling_control 2 bit • adaptation_field_control 2 bit • continuity_counter 4 bit • TS packet storage • Backward compatible mode using section/PES filters • Automatic storage using simple/repeated mode

  12. Splice Management Operation • Splice countdown received in PES adaptation field • AF posted to buffer, S/W receives DPR interrupt • Demux begins splice countdown for audio or video PID • S/W should: • enable splicing • extract new PID and program the Splicing Audio or Video PID • enable the Splice interrupt • When splice count = 0, new PID value is loaded by hardware

  13. PID Monitoring • PID Index Monitor • TACTSTAT0/1 registers • Provides status bit (and optional interrupt) • Set when a TS packet passes a given PID index • Status provided for 32 PIDs plus the PCR PID • Scrambling State Monitor • TSCRSTAT0/1 registers • Provides scrambling state for first 32 PID indexes • Two bits provided (in separate registers) • Can be TS or PES scrambling state

  14. NDS Conditional Access Module • Conditional access scheme used by BSky and others • ICAM Version 2.0 is implemented in SC2005 • LSI implementation requires certification by NDS • Includes: • CAM - Conditional Access Module • UART - actually this is a SmartCard • Demux ECM and EMM filters

  15. Demux support for NDS CAM/UART • 6 ECM PID filters and 1 EMM PID filter. • 6 cyclic buffers for ECM and 1 cyclic buffer for EMM • in addition to the 33 buffers from the SC2000 (32 general purpose, one for adaptation field). • Addition of NDS-specific EMM filtering and buffer overflow management • Descrambler enhancements for NDS • The ECM detector block • moved from the descrambler input to output to deal with scrambled ECM TID fields. • Entire ECM/EMM packets are posted (after passing filter)

  16. DVB Descrambler Features • Capable of descrambling various packet types • PSI, PRV, DPS, PES • Supports Transport Level descrambling • Supports PES Level descrambling • Supports Private data descrambling • Supports 12 pairs of 64-bit odd and even keys • Descrambling disabled when Transport is not locked • Assumes recommendations from the TM-1244 Rev.4 are met

  17. DVB Descrambler Operation • Transport Level Descrambling is performed on any packet whose PID table entry is programmed to be PES type or PRV type packets • If there is no TS Level scrambling, PES level scrambling is checked • Constant processing latency for scrambled and non-scrambled packets. • Each new key is loaded only at transport packet boundary • After lock the Scrambling Control bits are checked • Key must remain unaltered for the duration of the PES Packet

  18. Descrambler Rules • For PSI level scrambling, the Section Header and Pointer field are not scrambled • For PSI level scrambling, the CRC is not scrambled • For Private Data level scrambling all bytes shall be descrambled • Blocking Scrambled Data Mode ensures that only non scrambled A/V streams are passed to the A/V sub-systems

  19. Descrambler Key Table • 12 pairs of odd/even keys • Each key is 64-bits • Software programs odd key while even key is in use • Same scenario applies for even key • Key is selected via Key Index in PID Control register • Key indexes 12 to 15 are “pass-through” keys

  20. A/V Blocking • Enabled by setting the AUDEN or VIDEN bits in the Blocking A/V Stream Control register • PES data is not passed to A/V decoder if: • AUDEN or VIDEN bits are set • Stream is scrambled • Key index is set to pass-through (key index 12 to 15)

  21. PID Postprocessor Overview • Packet validation • Section filter • PES header filters • ECM filters • CRC checking • Payload posting options

  22. PID Postprocessor • Packet validation • Sync with start of TS packet (PUSI) and supports packets spanned across packet boundary. • Stream-level error detection • Packet lost error (Discontinuity) • CRC32 error

  23. Section Filters • 32 independent filters, each has 12 pairs of match/mask filters • Logical OR of multiple filters • Filter polarity controlled by NEG bit in Filter Match/Mask register • Logical OR of positive and negative filters (any number) • Logical AND of filter pairs • Logical AND of positive/negative filter pair • Filter polarity controlled by TCPFILPOL register • Multiple filter pairs are logically ORed • Cyclic buffers for section filters • Cyclic buffer index can be tied to PID or filter index • More discussion in dispatcher section

  24. Section Filter Diagram

  25. PES Header Filters • Known as Level 3 in Canal+ • Four filters provided for: • Flag fields • Trick mode fields • PTS range • DTS range • Filter match is a logical AND of all four filters

  26. PES Header Filters (cont.) • Match/mask filters for: • Flags field (8 bits) • PTS_DTS_flags 2 bits • ESCR_flag 1 bit • ES_rate_flag 1 bit • DSM_trick_mode_flag 1 bit • additional_copy_info_flag 1 bit • PES_CRC_flag 1 bit • PES_extension_flag 1 bit • DSM_trick_mode fields

  27. PES Header Filters (cont.) • Range filters (min and max) for: • PTS fields • DTS fields • If PES header filters match: • A/V PES data is sent to the A/V decoder • Non-A/V PES is posted to the cyclic buffer • DPR interrupt is generated after last PES byte is posted

  28. Summary of Level 2 and 3 Filters

  29. ECM Filters • Allows selective transfer of new ECM information • Filters out repeated ECM messages • Up to 6 independent filters (Odd, Even, Both or No ECM packets) • Filter operates on any Transport Packet with the ISECM bit set • Two modes of operation - Manual and Auto • In Manual mode, the user controls the ECM filtering through software • In Auto mode, the hardware controls the toggling of the Odd/Even ECM bits

  30. CRC Checking • CRC checking available for PSI, DPR and PRV packets • Not supported for A/V PES • CRC checking is enabled: • automatically for PSI packets with section_syntax_indicator = 1 • when CRCE bit is set in PID Control register • In case of a CRC error: • packet is posted if CRCSEND bit is set in PID Control register • interrupt is generated; TCRCERR contains PID and filter index

  31. Payload Posting Options • Entire TS packet after TS header filtering • selected by bits in the PID Control register • A/V PES data • sent directly to A/V decoder • Private PES • Level 2 and 3 filters available • DMA length selection for PES data • configured in the CPFDMALEN register • PSI section data • PRV packets • option to wait for PUSI or post immediately • Adaptation fields - dedicated buffer for all PIDs

  32. Adaptation Field Processing • Hardware processing for: • AFL - Adaptation Field Length • DI - Discontinuity Indicator • CC checking is disabled • RAI - Random Access Indicator • SPI and Splice Countdown values • PCR - see following section • Posting is enabled via the AF bit in the PID Control register

  33. Dispatcher Features • 33 cyclic buffers • Buffers can be attached to PID or filter indexes • Cyclic buffer management • 32 Cyclic buffers with associated address pointers • Cyclic buffer 33 is dedicated for Adaptation Fields • Address pointers are automatically reset on errors (CRC32, section filter mismatch)

  34. Cyclic Buffer Attachment Options • Software must ensure that first section filter byte is unique • Software must allocate buffers for PIDs and filters separately

  35. Dispatcher Interrupts • Dispatcher interrupts • Buffer index register or Dispatcher Interrupt Status • Generates interrupts in the following cases: • Reaches the end of a section • LAR is updated to end of section • Software must store previous LAR to know where section starts • Receives last byte of PES packet

  36. A/V Decoder Interface • OCU (Output Control Unit) • 512 byte buffers for audio and video PES • Internal parallel interface to A/V decoder • internal flow control prevents buffer underrun/overruns • A/V Control register must be set to 0x27 for proper operation

  37. Demux Pipeline and Dispatcher Flush • Demux pipeline flush mechanism • Auto flush: flush pipeline when a non-match PID packet • Timer flush: inserts dummy bytes into pipeline after hardware timeout • timeout resolution in bytes or packets • Dispatcher flush • Sets SDRAM threshold to 1 to flush out packet bytes • Triggered on user-programmable timeout

  38. Program Clock Reference Recovery

  39. Aux Input/Output Port • Bi-directional high speed parallel port • Shares the same pins as the IEEE 1284 port • Allows output of user selected transport packet(s) • Input channel for transport stream • Can be connected to a 1394 interface to send/receive MPEG-2 packets from other consumer devices

  40. Aux Output Mode • Aux output is enabled by AUX_DIR pin or DIR bit • A 5-bit Aux Index is output for each PID selected • Aux output clock options: 6.75, 13.5, 27 MHz

  41. Aux Input Mode • Aux data input is synchronized with the AUXCLK input • Maximum input frequency is 13.5 MHz

  42. Demux Host Interface • Register base address: 0xBE30.0000 • All registers 32-bits wide • Interrupts • One interrupt provided to interrupt controller subsystem • Two Status/Enable/Acknowledge registers provided • General demux interrupts • Dispatcher interrupts • Supporting registers • Packet Lost, CRC Error, Pending Cyclic Buffer Index

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