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361 Computer Architecture Lecture 12: Designing a Pipeline Processor

361 Computer Architecture Lecture 12: Designing a Pipeline Processor. Overview of a Multiple Cycle Implementation. The root of the single cycle processor’s problems: The cycle time has to be long enough for the slowest instruction Solution: Break the instruction into smaller steps

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361 Computer Architecture Lecture 12: Designing a Pipeline Processor

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  1. 361Computer ArchitectureLecture 12: Designing a Pipeline Processor

  2. Overview of a Multiple Cycle Implementation • The root of the single cycle processor’s problems: • The cycle time has to be long enough for the slowest instruction • Solution: • Break the instruction into smaller steps • Execute each step (instead of the entire instruction) in one cycle • Cycle time: time it takes to execute the longest step • Keep all the steps to have similar length • This is the essence of the multiple cycle processor • The advantages of the multiple cycle processor: • Cycle time is much shorter • Different instructions take different number of cycles to complete • Load takes five cycles • Jump only takes three cycles • Allows a functional unit to be used more than once per instruction

  3. Target 32 0 Mux 0 Mux 1 ALU 0 1 Mux 32 1 ALU Control Mux 1 0 << 2 Extend 16 Multiple Cycle Processor PCWr PCWrCond PCSrc BrWr • MCP: A functional unit to be used more than once per instruction Zero ALUSelA IorD MemWr IRWr RegDst RegWr 1 Mux 32 PC 0 Zero 32 Rs Ra 32 RAdr 5 32 Rt Rb busA 32 Ideal Memory 32 Instruction Reg Reg File 5 32 4 Rt 0 Rw 32 WrAdr 32 1 32 Rd Din Dout busW busB 32 2 32 3 Imm 32 ALUOp ExtOp MemtoReg ALUSelB

  4. Outline of Today’s Lecture • Recap and Introduction • Introduction to the Concept of Pipelined Processor • Pipelined Datapath and Pipelined Control • How to Avoid Race Condition in a Pipeline Design? • Pipeline Example: Instructions Interaction • Summary

  5. Pipelining is Natural! • Laundry Example • Sammy, Marc, Griffy, Alberteach have one load of clothes to wash, dry, and fold • Washer takes 30 minutes • Dryer takes 30 minutes • “Folder” takes 30 minutes • “Stasher” takes 30 minutesto put clothes into drawers A B C D

  6. A B C D Sequential Laundry 2 AM 12 6 PM 1 8 7 11 10 9 • Sequential laundry takes 8 hours for 4 loads • If they learned pipelining, how long would laundry take? 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 T a s k O r d e r Time

  7. 30 30 30 30 30 30 30 A B C D Pipelined Laundry: Start work ASAP 2 AM 12 6 PM 1 8 7 11 10 9 • Pipelined laundry takes 3.5 hours for 4 loads! Time T a s k O r d e r

  8. 30 30 30 30 30 30 30 A B C D Pipelining Lessons 6 PM 7 8 9 • Pipelining doesn’t help latency of single task, it helps throughput of entire workload • Multiple tasks operating simultaneously using different resources • Potential speedup = Number pipe stages • Pipeline rate limited by slowest pipeline stage • Unbalanced lengths of pipe stages reduces speedup • Time to “fill” pipeline and time to “drain” it reduces speedup • Stall for Dependences Time T a s k O r d e r

  9. Why Pipeline? • Suppose we execute 100 instructions • Single Cycle Machine • 45 ns/cycle x 1 CPI x 100 inst = 4500 ns • Multicycle Machine • 10 ns/cycle x 4.6 CPI (due to inst mix) x 100 inst = 4600 ns • Ideal pipelined machine • 10 ns/cycle x (1 CPI x 100 inst + 4 cycle drain) = 1040 ns

  10. Timing Diagram of a Load Instruction Instruction Fetch Instr Decode / Address Data Memory Reg Wr Reg. Fetch Clk Clk-to-Q Old Value New Value PC Instruction Memory Access Time Rs, Rt, Rd, Op, Func Old Value New Value Delay through Control Logic ALUctr Old Value New Value ExtOp Old Value New Value ALUSrc Old Value New Value RegWr Old Value New Value Register File Access Time busA Old Value New Value Delay through Extender & Mux Register File Write Time busB Old Value New Value ALU Delay Address Old Value New Value Data Memory Access Time busW Old Value New

  11. Ifetch Reg/Dec Exec Mem Wr The Five Stages of Load Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 • Ifetch: Instruction Fetch • Fetch the instruction from the Instruction Memory • Reg/Dec: Registers Fetch and Instruction Decode • Exec: Calculate the memory address • Mem: Read the data from the Data Memory • Wr: Write the data back to the register file Load

  12. 1st lw Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Pipelining the Load Instruction Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Clock • The five independent functional units in the pipeline datapath are: • Instruction Memory for the Ifetch stage • Register File’s Read ports (bus A and busB) for the Reg/Dec stage • ALU for the Exec stage • Data Memory for the Mem stage • Register File’s Write port (bus W) for the Wr stage • One instruction enters the pipeline every cycle • One instruction comes out of the pipeline (complete) every cycle • The “Effective” Cycles per Instruction (CPI) is 1 2nd lw 3rd lw

  13. IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB IFetch Dcd Exec Mem WB Conventional Pipelined Execution Representation Time Program Flow

  14. Ifetch Reg Exec Mem Wr Ifetch Reg Exec Mem Ifetch Ifetch Reg Exec Mem Wr Ifetch Reg Exec Mem Wr Ifetch Reg Exec Mem Wr Single Cycle, Multiple Cycle, vs. Pipeline Cycle 1 Cycle 2 Clk Single Cycle Implementation: Load Store Waste Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Clk Multiple Cycle Implementation: Load Store R-type Pipeline Implementation: Load Store R-type

  15. Im Dm Reg Reg ALU Im Dm Reg Reg ALU Im Dm Reg Reg ALU Im Dm Reg Reg ALU Im Dm Reg Reg ALU Why Pipeline? Because the resources are there! Time (clock cycles) I n s t r. O r d e r Inst 0 Inst 1 Inst 2 Inst 3 Inst 4

  16. Can pipelining get us into trouble? • Yes:Pipeline Hazards • structural hazards: attempt to use the same resource two different ways at the same time • E.g., combined washer/dryer would be a structural hazard or folder busy doing something else (watching TV) • data hazards: attempt to use item before it is ready • E.g., one sock of pair in dryer and one in washer; can’t fold until get sock from washer through dryer • instruction depends on result of prior instruction still in the pipeline • control hazards: attempt to make a decision before condition is evaulated • E.g., washing football uniforms and need to get proper detergent level; need to see after dryer before next load in • branch instructions • Can always resolve hazards by waiting • pipeline control must detect the hazard • take action (or delay action) to resolve hazards

  17. Mem ALU Mem Mem Reg Reg ALU Mem Mem Reg Reg ALU ALU Mem Mem Reg Reg ALU Single Memory is a Structural Hazard Time (clock cycles) I n s t r. O r d e r Mem Reg Reg Load Instr 1 Instr 2 Mem Mem Reg Reg Instr 3 Instr 4 Detection is easy in this case! (right half highlight means read, left half write)

  18. Structural Hazards limit performance • Example: if 1.3 memory accesses per instruction and only one memory access per cycle then • average CPI  1.3 • otherwise resource is more than 100% utilized • More on Hazards later

  19. Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Wr Pipelining the R-type and Load Instruction Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Clock • We have a problem: • Two instructions try to write to the register file at the same time! Ops! We have a problem! R-type R-type Load R-type R-type

  20. Ifetch Reg/Dec Exec Wr The Four Stages of R-type Cycle 1 Cycle 2 Cycle 3 Cycle 4 • Ifetch: Instruction Fetch • Fetch the instruction from the Instruction Memory • Reg/Dec: Registers Fetch and Instruction Decode • Exec: ALU operates on the two register operands • Wr: Write the ALU output back to the register file R-type

  21. 1 2 3 4 5 Load Ifetch Reg/Dec Exec Mem Wr 1 2 3 4 R-type Ifetch Reg/Dec Exec Wr Important Observation • Each functional unit can only be used once per instruction • Each functional unit must be used at the same stage for all instructions: • Load uses Register File’s Write Port during its 5th stage • R-type uses Register File’s Write Port during its 4th stage

  22. Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Solution 1: Insert “Bubble” into the Pipeline Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Clock • Insert a “bubble” into the pipeline to prevent 2 writes at the same cycle • The control logic can be complex • No instruction is completed during Cycle 5: • The “Effective” CPI for load is >1 Load R-type Pipeline R-type R-type Bubble

  23. Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Mem Exec Wr Ifetch Reg/Dec Mem Exec Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Mem Exec Wr Ifetch Reg/Dec Mem Exec Wr Solution 2: Delay R-type’s Write by One Cycle • Delay R-type’s register write by one cycle: • Now R-type instructions also use Reg File’s write port at Stage 5 • Mem stage is a NOOP stage: nothing is being done 1 2 3 4 5 R-type Mem Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Clock R-type R-type Load R-type R-type

  24. Ifetch Reg/Dec Exec Mem The Four Stages of Store Cycle 1 Cycle 2 Cycle 3 Cycle 4 • Ifetch: Instruction Fetch • Fetch the instruction from the Instruction Memory • Reg/Dec: Registers Fetch and Instruction Decode • Exec: Calculate the memory address • Mem: Write the data into the Data Memory Store Wr

  25. Ifetch Reg/Dec Exec Mem The Four Stages of Beq Cycle 1 Cycle 2 Cycle 3 Cycle 4 • Ifetch: Instruction Fetch • Fetch the instruction from the Instruction Memory • Reg/Dec: Registers Fetch and Instruction Decode • Exec: ALU compares the two register operands • Adder calculates the branch target address • Mem: If the registers we compared in the Exec stage are the same, • Write the branch target address into the PC Beq Wr

  26. 1 Mux 0 A Pipelined Datapath Clk Ifetch Reg/Dec Exec Mem Wr ExtOp ALUOp Branch RegWr 1 0 PC+4 PC+4 PC PC+4 Imm16 Imm16 Zero Data Mem Rs busA A Ra busB Exec Unit RA Do Rb IUnit IF/ID Register Ex/Mem Register Mem/Wr Register ID/Ex Register Rt WA RFile Di Rw Di Rt 0 I Rd 1 ALUSrc RegDst MemWr MemtoReg

  27. 1 Mux 0 The Instruction Fetch Stage You are here! • Location 10: lw $1, 0x100($2) $1 <- Mem[($2) + 0x100] Clk Ifetch Reg/Dec Exec Mem ExtOp ALUOp Branch RegWr 1 0 PC+4 PC+4 PC+4 Imm16 Imm16 PC = 14 Zero Data Mem Rs busA A Ra busB IF/ID: lw $1, 100 ($2) Exec Unit RA Do Rb IUnit Ex/Mem Register Mem/Wr Register ID/Ex Register Rt WA RFile Di Rw Di Rt 0 I Rd 1 ALUSrc RegDst MemWr MemtoReg

  28. Adder A Detail View of the Instruction Unit • Location 10: lw $1, 0x100($2) You are here! Clk Ifetch Reg/Dec 1 0 “4” PC = 14 10 IF/ID: lw $1, 100 ($2) Address Instruction Memory Instruction

  29. 1 Mux 0 The Decode / Register Fetch Stage You are here! • Location 10: lw $1, 0x100($2) $1 <- Mem[($2) + 0x100] Clk Ifetch Reg/Dec Exec Mem ExtOp ALUOp Branch RegWr 1 0 PC+4 PC+4 PC PC+4 Imm16 IF/ID: Imm16 Zero Data Mem Rs busA A Ra busB ID/Ex: Reg. 2 & 0x100 Exec Unit RA Do Rb IUnit Ex/Mem Register Mem/Wr Register Rt WA RFile Di Rw Di Rt 0 I Rd 1 ALUSrc RegDst MemWr MemtoReg

  30. 1 Mux 0 Load’s Address Calculation Stage You are here! • Location 10: lw $1, 0x100($2) $1 <- Mem[($2) + 0x100] Clk Ifetch Reg/Dec Exec Mem ALUOp=Add Branch RegWr ExtOp=1 1 0 PC+4 PC+4 PC PC+4 Imm16 IF/ID: Imm16 Zero Data Mem Rs busA A Ra busB Exec Unit RA Do Rb Ex/Mem: Load’s Address IUnit Mem/Wr Register ID/Ex Register Rt WA RFile Di Rw Di Rt 0 I Rd 1 ALUSrc=1 RegDst=0 MemWr MemtoReg

  31. Adder ALU Control A Detail View of the Execution Unit You are here! Clk Exec Mem << 2 Target 32 PC+4 32 busA Zero ID/Ex Register 32 Ex/Mem: Load’s Memory Address ALUout ALU busB 0 32 32 Mux imm16 ALUctr 3 Extender 1 16 32 3 ALUSrc=1 ExtOp=1 ALUOp=Add

  32. 1 Mux 0 Load’s Memory Access Stage You are here! • Location 10: lw $1, 0x100($2) $1 <- Mem[($2) + 0x100] Clk Ifetch Reg/Dec Exec Mem ExtOp ALUOp Branch=0 RegWr 1 0 PC+4 PC+4 PC PC+4 Imm16 IF/ID: Imm16 Zero Data Mem Rs busA A Ra busB Exec Unit RA Do Rb Mem/Wr: Load’s Data IUnit Ex/Mem Register ID/Ex Register Rt WA RFile Di Rw Di Rt 0 I Rd 1 ALUSrc RegDst MemWr=0 MemtoReg

  33. 1 Mux 0 Load’s Write Back Stage You are somewhere out there! • Location 10: lw $1, 0x100($2) $1 <- Mem[($2) + 0x100] Clk Ifetch Reg/Dec Exec Mem Wr ExtOp ALUOp Branch RegWr=1 1 0 PC+4 PC+4 PC PC+4 Imm16 IF/ID: Imm16 Zero Data Mem Rs busA A Ra busB Exec Unit RA Do Rb IUnit Ex/Mem Register Mem/Wr Register ID/Ex Register Rt WA RFile Di Rw Di Rt 0 I Rd 1 ALUSrc RegDst MemWr MemtoReg=1

  34. 1 Mux 0 How About Control Signals? • Key Observation: Control Signals at Stage N = Func (Instr. at Stage N) • N = Exec, Mem, or Wr • Example: Controls Signals at Exec Stage = Func(Load’s Exec) Ifetch Reg/Dec Exec Mem Wr ALUOp=Add Branch RegWr ExtOp=1 1 0 PC+4 PC+4 PC+4 Imm16 IF/ID: Imm16 PC Zero Data Mem Rs busA A Ra busB Exec Unit RA Do Rb Ex/Mem: Load’s Address IUnit Mem/Wr Register ID/Ex Register Rt WA RFile Di Rw Di Rt 0 I Rd 1 ALUSrc=1 RegDst=0 MemWr MemtoReg

  35. Pipeline Control • The Main Control generates the control signals during Reg/Dec • Control signals for Exec (ExtOp, ALUSrc, ...) are used 1 cycle later • Control signals for Mem (MemWr Branch) are used 2 cycles later • Control signals for Wr (MemtoReg MemWr) are used 3 cycles later Reg/Dec Exec Mem Wr ExtOp ExtOp ALUSrc ALUSrc ALUOp ALUOp Main Control RegDst RegDst Ex/Mem Register Mem/Wr Register IF/ID Register ID/Ex Register MemWr MemWr MemWr Branch Branch Branch MemtoReg MemtoReg MemtoReg MemtoReg RegWr RegWr RegWr RegWr

  36. Beginning of the Wr’s Stage: A Real World Problem Clk Clk • At the beginning of the Wr stage, we have a problem if: • RegAdr’s (Rd or Rt) Clk-to-Q > RegWr’s Clk-to-Q • Similarly, at the beginning of the Mem stage, we have a problem if: • WrAdr’s Clk-to-Q > MemWr’s Clk-to-Q • We have a race condition between Address and Write Enable! RegAdr WrAdr RegWr MemWr RegWr’s Clk-to-Q MemWr’s Clk-to-Q RegAdr’s Clk-to-Q WrAdr’s Clk-to-Q RegWr MemWr Mem/Wr Ex/Mem RegAdr WrAdr Reg File Data Memory Data Data

  37. Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr The Pipeline Problem • Multiple Cycle design prevents race condition between Addr and WrEn: • Make sure Address is stable by the end of Cycle N • Asserts WrEn during Cycle N + 1 • This approach can NOT be used in the pipeline design because: • Must be able to write the register file every cycle • Must be able write the data memory every cycle Clock Store Store R-type R-type

  38. Synchronize Register File & Synchronize Memory • Solution: And the Write Enable signal with the Clock • This is the ONLY place where gating the clock is used • MUST consult circuit expert to ensure no timing violation: • Example: Clock High Time > Write Access Delay Synchronize Memory and Register File Clk Address, Data, and WrEn must be stable at least 1 set-up time before the Clk edge I_Addr I_WrEn Write occurs at the cycle following the clock edge that captures the signals C_WrEn WrEn WrEn C_WrEn I_WrEn Address Reg File or Memory Data Reg File or Memory Address I_Addr Clk Data I_Data

  39. Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr A More Extensive Pipelining Example Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Clock • End of Cycle 4: Load’s Mem, R-type’s Exec, Store’s Reg, Beq’s Ifetch • End of Cycle 5: Load’s Wr, R-type’s Mem, Store’s Exec, Beq’s Reg • End of Cycle 6: R-type’s Wr, Store’s Mem, Beq’s Exec • End of Cycle 7: Store’s Wr, Beq’s Mem 0: Load 4: R-type 8: Store 12: Beq (target is 1000) End of Cycle 4 End of Cycle 5 End of Cycle 6 End of Cycle 7

  40. Clk 1 Mux 0 Clk MemWr=0 Pipelining Example: End of Cycle 4 • 0: Load’s Mem 4: R-type’s Exec 8: Store’s Reg 12: Beq’s Ifetch 8: Store’s Reg 4: R-type’s Exec 0: Load’s Mem 12: Beq’s Ifet ALUOp=R-type ExtOp=x Branch=0 RegWr=0 1 0 PC+4 PC+4 PC+4 Imm16 Imm16 PC = 16 Zero Data Mem Rs busA A Ra busB IF/ID: Beq Instruction Exec Unit RA Do Rb ID/Ex: Store’s busA & B Ex/Mem: R-type’s Result Mem/Wr: Load’s Dout IUnit Rt WA RFile Di Rw Di Rt 0 I Rd 1 ALUSrc=0 RegDst=1 MemtoReg=x

  41. Clk 1 Mux 0 Clk MemWr=0 Pipelining Example: End of Cycle 5 • 0: Lw’s Wr 4: R’s Mem 8: Store’s Exec 12: Beq’s Reg 16: R’s Ifetch 12: Beq’s Reg 8: Store’s Exec 4: R-type’s Mem 0: Load’s Wr 16: R’s Ifet ALUOp=Add ExtOp=1 Branch=0 RegWr=1 1 0 PC+4 PC+4 PC+4 Imm16 Imm16 PC = 20 Zero Data Mem Rs busA A Ra busB Exec Unit RA Do Rb Ex/Mem: Store’s Address IF/ID: Instruction @ 16 ID/Ex: Beq’s busA & B Mem/Wr: R-type’s Result IUnit Rt WA RFile Di Rw Di Rt 0 I Rd 1 RegDst=x MemtoReg=1 ALUSrc=1

  42. Clk 1 Mux 0 Clk MemWr=1 Pipelining Example: End of Cycle 6 • 4: R’s Wr 8: Store’s Mem 12: Beq’s Exec 16: R’s Reg 20: R’s Ifet 16: R-type’s Reg 12: Beq’s Exec 8: Store’s Mem 20: R-type’s Ifet 4: R-type’s Wr ALUOp=Sub ExtOp=1 Branch=0 RegWr=1 1 0 PC+4 PC+4 PC+4 Imm16 Imm16 PC = 24 Zero Data Mem Rs busA A Ra busB Exec Unit RA Do Rb Ex/Mem: Beq’s Results Mem/Wr: Nothing for St IF/ID: Instruction @ 20 ID/Ex:R-type’s busA & B IUnit Rt WA RFile Di Rw Di Rt 0 I Rd 1 RegDst=x MemtoReg=0 ALUSrc=0

  43. Clk 1 Mux 0 Clk MemWr=0 Pipelining Example: End of Cycle 7 • 8: Store’s Wr 12: Beq’s Mem 16: R’s Exec 20: R’s Reg 24: R’s Ifet 20: R-type’s Reg 16: R-type’s Exec 12: Beq’s Mem 24: R-type’s Ifet 8: Store’s Wr ALUOp=R-type ExtOp=x Branch=1 RegWr=0 1 0 PC+4 PC+4 PC+4 Imm16 Imm16 PC = 1000 Zero Data Mem Rs busA A Ra busB Exec Unit RA Do Rb Ex/Mem: Rtype’s Results IF/ID: Instruction @ 24 ID/Ex:R-type’s busA & B Mem/Wr:Nothing for Beq IUnit Rt WA RFile Di Rw Di Rt 0 I Rd 1 RegDst=1 MemtoReg=x ALUSrc=0

  44. Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr The Delay Branch Phenomenon Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Cycle 11 Clk • Although Beq is fetched during Cycle 4: • Target address is NOT written into the PC until the end of Cycle 7 • Branch’s target is NOT fetched until Cycle 8 • 3-instruction delay before the branch take effect • This is referred to as Branch Hazard: • Clever design techniques can reduce the delay to ONE instruction 12: Beq (target is 1000) 16: R-type 20: R-type 24: R-type 1000: Target of Br

  45. Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr The Delay Load Phenomenon Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Clock • Although Load is fetched during Cycle 1: • The data is NOT written into the Reg File until the end of Cycle 5 • We cannot read this value from the Reg File until Cycle 6 • 3-instruction delay before the load take effect • This is referred to as Data Hazard: • Clever design techniques can reduce the delay to ONE instruction I0: Load Plus 1 Plus 2 Plus 3 Plus 4

  46. Summary • Disadvantages of the Single Cycle Processor • Long cycle time • Cycle time is too long for all instructions except the Load • Multiple Clock Cycle Processor: • Divide the instructions into smaller steps • Execute each step (instead of the entire instruction) in one cycle • Pipeline Processor: • Natural enhancement of the multiple clock cycle processor • Each functional unit can only be used once per instruction • If a instruction is going to use a functional unit: • it must use it at the same stage as all other instructions • Pipeline Control: • Each stage’s control signal depends ONLY on the instruction that is currently in that stage

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