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Integrating 1553 Avionics Bus Hardware Into ELV Simulation Model

This thesis aims to integrate a 1553 avionics bus into a NASA Matlab/Simulink rocket launch simulation, allowing analysts to test flight hardware. It covers prototype, findings, message formats, and more.

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Integrating 1553 Avionics Bus Hardware Into ELV Simulation Model

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  1. Integrating 1553 Avionics Bus Hardware Into ELV Simulation Model by Elias Victor for Florida Institute of Technology (FIT) School of Electrical and Computer Engineering (ECE) Master’s Thesis Committee by Elias Victor (6112)

  2. Study Purpose • To integrate a MIL-STD-1553 avionics bus into an existing NASA Matlab/Simulink rocket launch simulation. • To show that the original simulation results can be duplicated using the 1553 integrated solution. • To give mission analysts the capability to test actual flight hardware and software. by Elias Victor (6112)

  3. Choice Definitions • Simulink: along with Matlab, Simulink is a Mathworks, Inc. product that allows for the simulation, modeling and analysis of dynamic systems. Simulink is provided with an extensive library of blocks that can be used to simulate many common system behaviors, but also allows for the creation of your own custom blocks. • UCAT: Universal Controls and Analysis Tool • S-function: a custom Simulink block made up of function callbacks that are called at different times during simulation execution. • Triggered Subsystem: Simulink block that executes when a trigger event occurs. • 1553 Data Bus: a common avionics data bus composed of cables, couplers and terminators. • 1553 Word: a 16-bit sequence plus sync and parity. • Bus Controller: terminal in charge of initiating message transfers on the 1553 bus. • Remote Terminal: terminal that operates as a slave on the 1553 bus servicing bus controller requests. by Elias Victor (6112)

  4. Outline • Prototype Description • Demo integrated 1553 simulation startup • Integrated Components • Control System • Message Formats • Message Exchange • S-function Callbacks • Hurdles Overcome • Findings of Interest • Further Study Possibilities • Conclusion • Results Comparison by Elias Victor (6112)

  5. Prototype Description by Elias Victor (6112)

  6. Demo Start integrated 1553 simulation. by Elias Victor (6112)

  7. Integrated Components by Elias Victor (6112)

  8. Integrated Components by Elias Victor (6112)

  9. Integrated Components by Elias Victor (6112)

  10. Integrated Components by Elias Victor (6112)

  11. Integrated Components by Elias Victor (6112)

  12. Integrated Components by Elias Victor (6112)

  13. Control System (original) NOTE: Details of simulation blocks’ internals have been omitted for proprietary reasons. by Elias Victor (6112)

  14. Control System (integrated) ucatrt = remote terminal ucatbc = bus controller NOTE: Details of simulation blocks’ internals have been omitted for proprietary reasons. by Elias Victor (6112)

  15. Message Formats d = data, u = unused/reserved, cnt = count, csum = checksum by Elias Victor (6112)

  16. Message Formats d = data, u = unused/reserved, cnt = count, csum = checksum by Elias Victor (6112)

  17. Message Exchange by Elias Victor (6112)

  18. Message Exchange by Elias Victor (6112)

  19. Message Exchange by Elias Victor (6112)

  20. Message Exchange by Elias Victor (6112)

  21. Message Exchange by Elias Victor (6112)

  22. Message Exchange by Elias Victor (6112)

  23. Message Exchange by Elias Victor (6112)

  24. S-function Callbacks by Elias Victor (6112)

  25. Hurdles Overcome • Gathering prototype hardware and software • 1553 transmission racing conditions • Accelerated vs. Normal • SBS reference library correction • C compiler differences (VCC vs. LCC) by Elias Victor (6112)

  26. Findings of Interest • Performance impact: • Average elapsed-times in real-time seconds based on 10 consecutive runs of each simulation: • Original simulation = 8,768.5 • Integrated 1553 simulation = 9,503.1 • Difference: 9503.1 - 8768.5 = 734.6 • Degradation: ( 734.6 / 8,768.5 ) * 100% = 8.4% • Acceptable considering benefits by Elias Victor (6112)

  27. Findings of Interest (continued) “accelerated” is NOT “normal” NOTE: actual yaw and pitch variables renamed to VAR2 for proprietary reasons by Elias Victor (6112)

  28. Findings of Interest (continued) All compilers are NOT created equal. NOTE: actual yaw and pitch variables renamed to VAR2 for proprietary reasons by Elias Victor (6112)

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