TRIPENT

1. TRIPENT David Yip, Charles Moore, Koushik Subramanian, Chris Meyer, Eric Knutson

2. Naming Scheme • Tri – Latin for three • Pent – Greek for five • There are three five bit sections for instructions, hence TriPent

3. Architecture There are 2 types of instructions

4. I-Type • - If the I-Type instruction holds a memory address, the least significant bit is omitted (all addresses are word-aligned, and thus the last bit will be 0). • - If the I-Type instruction holds any other immediate, the most significant bit is omitted, assembler uses of the LON instruction (sets the most significant bit in $IR)

5. R-Type • Opcodes are only defined for R-Type instructions, as only one instruction, lir, deals directly with immediate values.

6. Registers $28: $IR, immediate register1 $29: $RA, return address register (used for procedure calls) $30: $AT, reserved for use by the assembler $31: $SP, stack pointer (used by PUSH / POP pseudoinstructions) TIP - $s0-$s7 should be preserved across procedure calls

7. I/O ports • (5) 16-bit input ports • (1) 16-bit output port

8. Interrupt Handling • Vectored interrupt model with 8 interrupt service lines. • Addresses of interrupt handlers are memory-mapped at fixed locations. • Memory mapping is accomplished through use of the SW (store word) instruction.

9. Arithmetic • ADD – $RD,$RS R-Type • ADD – $RD,IMM Psuedo • SUB – $RD,$RS R-Type • SUB – $RD,IMM Psuedo

10. Logical • AND – $RD,$RS R-Type • AND – $RD,IMM Psuedo • OR – $RD,$RS R-Type • OR – $RD,IMM Psuedo • XOR – $RD,$RS R-Type • XOR – $RD,IMM Psuedo

11. Logical (continued) • SHL – $RD,$AMT R-Type • SHL – $RD,IMM Psuedo • SHR – $RD,$AMT R-Type • SHR – $RD,IMM Psuedo

12. Comparison • CMPE – $RD,$RS R-Type • CMPL – $RD,$RS R-Type • Result will be set in $ST as a 1 or 0

13. Load/Store • LIR IMM I-Type • LON R-Type • LA $RD,LABEL Pseudo • LW $RD,$RS R-Type • LW $RD,E($RS) Pseudo

14. Load/Store (continued) • SW $RD,$RS R-Type • SW $RD,E($RS) Pseudo • MOV $RD,$RS Pseudo • MOV $RD,IMM Pseudo • PUSH $RS Pseudo • PUSH IMM Pseudo • POP $RD Pseudo

15. Branch and Jump • BNE $RD,$RS,LABEL Pseudo • BEQ $RD,$RS,LABEL Pseudo • BLT $RD,$RS,LABEL Pseudo • BGT $RD,$RS,LABEL Pseudo • BNE $RD,IMM,LABEL Pseudo • BEQ $RD,IMM,LABEL Pseudo

16. Branch and Jump (continued) • BLT $RD,IMM,LABEL Pseudo • BGT $RD,IMM,LABEL Pseudo • JZ LABEL Pseudo • JNZ LABEL Pseudo • JZ $RD R-Type • JNZ $RD R-Type

17. Branch and Jump (continued) • JAL $RD R-Type • JAL LABEL Pseudo • J LABEL Pseudo • J $RD R-Type

18. Input/Output • INP $RD,Port Pseudo • INP $RD,$RP Pseudo • OUTP PORT,$RS Pseudo • OUTP $RP,$RS Pseudo

19. Statistics • Gate Count – 14,405 • Minimum period – 21.791ns • Max Frequency – 45.891 mhz • Number of Cycles – 644813 (cycles to find first relative prime for 5040 including time to setup input)

20. Recursive • Implemented our greatest common denominator algorithm using a recursive procedure. Thus proving that our processor can handle recursive calls.

21. Direct Addressing • Up to 216 bits of memory can be directly addressed • Eliminates need for superfluous shifting since the entire address can be represented

22. Status Register • The Status Register is a ‘scratch’ register that is holds pieces of state/status information. It contains 3 1-bit registers: comparison result register, pending interrupt register, interrupt enable register; as well as 1 3-bit register to hold a number (0-7) that specifies the current interrupt line waiting to be serviced.

23. Barrel Shifter • Contains 32 1-bit shifters that run in series with each shifter output going into a 32-bit multiplexer. Output is then obtained depending on how many shifts needed.