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CPRE 583 Reconfigurable Computing (VHDL Overview )

CPRE 583 Reconfigurable Computing (VHDL Overview ). Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA. http://class.ece.iastate.edu/cpre583/. VHDL basics. VHDL: ( V )HSIC ( H )ardware ( D )escription ( L )anguage

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CPRE 583 Reconfigurable Computing (VHDL Overview )

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  1. CPRE 583Reconfigurable Computing(VHDL Overview ) Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http://class.ece.iastate.edu/cpre583/

  2. VHDL basics • VHDL: (V)HSIC (H)ardware (D)escription (L)anguage • VHSIC: (V)ery (H)igh (S)peed (I)ntegrated (C)ircuit • It is NOT a programming language!!! • It is a Hardware Description Language (HDL) • Conceptually VERY different form C,C++

  3. Some Key Differences from C • C is inherently sequential (serial), one statement executed at a time • VHDL is inherently concurrent (parallel), many statements execute (simulate) at a time

  4. Some Key Differences from C VHDL example C example Initially: A,B,C,X,Y,Z,Ans =1 A = B + C X = Y + Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

  5. Some Key Differences from C VHDL example C example Initially: A,B,C,X,Y,Z,Ans =1 A = B + C X = Y + Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

  6. Some Key Differences from C VHDL example C example Initially: A,B,C,X,Y,Z,Ans =1 A = B + C X = Y + Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 1 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

  7. Some Key Differences from C VHDL example C example Initially: A,B,C,X,Y,Z,Ans =1 A = B + C X = Y + Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

  8. Some Key Differences from C VHDL example C example Initially: A,B,C,X,Y,Z,Ans =1 A = B + C X = Y + Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 Show impact Of changing Order of statements

  9. Some Key Differences from C VHDL example C example Initially: A,B,C,X,Y,Z,Ans =1 Snap shot after input change A = B + C X = Y + Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

  10. Some Key Differences from C VHDL example C example Initially: A,B,C,X,Y,Z,Ans =1 A = B + C X = Y + Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 2

  11. Some Key Differences from C VHDL example C example Initially: A,B,C,X,Y,Z,Ans =1 A = B + C X = Y + Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 2 Different

  12. Some Key Differences from C VHDL example C example Initially: A,B,C,X,Y,Z,Ans =1 Snap shot after input change A = B + C X = Y + Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 2

  13. Some Key Differences from C VHDL example C example Initially: A,B,C,X,Y,Z,Ans =1 A = B + C X = Y + Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 2

  14. Some Key Differences from C VHDL example C example Initially: A,B,C,X,Y,Z,Ans =1 A = B + C X = Y + Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4

  15. Corresponding circuit VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step”

  16. Corresponding circuit VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” B(1) + A(1) C(1) + Ans(1) Y(1) + X(1) Z(1)

  17. Corresponding circuit VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” B(1) + A(2) C(1) + Ans(2) Y(1) + X(2) Z(1)

  18. Corresponding circuit VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” B(1) + A(2) C(1) + Ans(4) Y(1) + X(2) Z(1)

  19. Corresponding circuit (More realistic) VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C after 2ns X <= Y + Z after 2ns Ans <= A + X after 2ns “Simulates in parallel ever delta time step” B(1) + A(1) C(1) 2ns + Ans(1) Y(1) 2ns + X(1) Z(1) 2ns

  20. Corresponding circuit (More realistic) VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C after 2ns X <= Y + Z after 2ns Ans <= A + X after 2ns “Simulates in parallel ever delta time step” B(1) + A(2) C(1) 2ns + Ans(2) Y(1) 2ns + X(2) Z(1) 2ns

  21. Corresponding circuit (More realistic) VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C after 2ns X <= Y + Z after 2ns Ans <= A + X after 2ns “Simulates in parallel ever delta time step” B(1) + A(2) C(1) 2ns + Ans(4) Y(1) 2ns + X(2) Z(1) 2ns

  22. Typical Structure of a VHDL File Include Libraries LIBRARY ieee; ENTITY test_circuit IS PORT(B,C,Y,Z,Ans); END test_circuit; ARCHITECTURE structure OF test_circuit IS signal A : std_logic_vector(7 downto 0); signal X : std_logic_vector(7 downto 0); BEGIN A <= B + C; X <= Y + Z; Ans <= A + X; END Define component name and Input/output ports Declare internal signals, components Implement components functionality

  23. Process • Process provide a level serialization in VHDL (e.g. variables, clocked processes) • Help separate and add structure to VHDL design

  24. Process Example BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin A <= B + C; X <= Y + Z; Ans <= A + X; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin A <= B + 1; X <= B + Y; Ans2 <= Ans1 + X; End My_process_2; END; Sensitivity list: specify inputs to the process. Process is updated when a specified input changes

  25. Process Example (Multiple Drivers) BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin A <= B + C; X <= Y + Z; Ans <= A + X; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin A <= B + 1; X <= B + Y; Ans2 <= Ans1 + X; End My_process_2; END; A signal can only be Driven (written) by one process. But can be read by many Compile or simulator may give a “multiple driver” Error or Warning message

  26. Process Example (Multiple Drivers) BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin A <= B + C; X <= Y + Z; Ans <= A + X; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin A1 <= B + 1; X1 <= B + Y; Ans2 <= Ans1 + X; End My_process_2; END; Maybe A,X were suppose to be A1,X1. Cut and paste error. Or may need to rethink Hardware structure to remove multiple driver issue.

  27. Process Example (if-statement) BEGIN My_process_1 : process (A,B,C,X,Y,Z) Begin if (B = 0) then C <= A + B; Z <= X + Y; Ans1 <= A + X; else C <= 1; Z <= 0; Ans1 <= 1; end if; End My_process_1; END; Add circuit

  28. Clock Process Example BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; End My_process_1; END; circuit not clocked A() or C() B() and Ans() X() or Z() Y()

  29. Clock Process Example BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; End My_process_1; END; D Flip-Flop DFF Register circuit with clock A() or C() B() and Ans() X() Z() or Y() clk

  30. Clock Process Example BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A or B; Z <= X or Y; Ans <= C and Z; END IF; End My_process_1; END; circuit with clock A() or C() B() Ans() and X() Z() or Y() clk

  31. Clock Process Example 2 BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A xor B; Z <= X or Y; Ans <= C xor Z; END IF; End My_process_1; END; circuit with clock A() xor C() B() Ans() xor X() Z() or Y() clk

  32. Clock Process Example 2 (Answer) BEGIN My_process_1 : process (clk) Begin IF (clk’event and clk = ‘1’) THEN C <= A xor B; Z <= X or Y; Ans <= C xor Z; END IF; End My_process_1; END; circuit with clock A() xor C() B() Ans() xor X() Z() or Y() clk

  33. VHDL Constructs • Entity • Process • Signal, Variable, Constants, Integers • Array, Record • VHDL on-line tutorials: • http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html • http://www.vhdl-online.de/tutorial/

  34. Signals and Variables • Signals • Updated at the end of a process • Have file scope • Variables • Updated instantaneously • Have process scope • VHDL on-line tutorials: • http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html • http://www.vhdl-online.de/tutorial/

  35. std_logic, std_logic_vector • Very common data types • std_logic • Single bit value • Values: U, X, 0, 1, Z, W, H, L, - • Example: signal A : std_logic; • A <= ‘1’; • Std_logic_vector: is an array of std_logic • Example: signal A : std_logic_vector (4 downto 0); • A <= x“00Z001” • VHDL on-line tutorials: • http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html • http://www.vhdl-online.de/tutorial/

  36. Std_logic values • Std_logic values • U : Uninitialized (signal has not been assigned a value yet) • X : Unknow (2 drivers one ‘0’ one ‘1’) • H : weak ‘1’ (example: model pull-up resister) • I have never used this value • L : weak ‘0’ Time step 0

  37. Std_logic values • Std_logic values • U : Uninitialized (signal has not been assigned a value yet) • X : Unknow (2 drivers one ‘0’ one ‘1’) • H : weak ‘1’ (example: model pull-up resister) • I have never used this value • L : weak ‘0’ 1 U U U Time step 0

  38. Std_logic values • Std_logic values • U : Uninitialized (signal has not been assigned a value yet) • X : Unknow (2 drivers one ‘0’ one ‘1’) • H : weak ‘1’ (example: model pull-up resister) • I have never used this value • L : weak ‘0’ 0 1 U U Time step 1

  39. Std_logic values • Std_logic values • U : Uninitialized (signal has not been assigned a value yet) • X : Unknow (2 drivers one ‘0’ one ‘1’) • H : weak ‘1’ (example: model pull-up resister) • I have never used this value • L : weak ‘0’ 1 0 1 U Time step 2

  40. Std_logic values • Std_logic values • U : Uninitialized (signal has not been assigned a value yet) • X : Unknow (2 drivers one ‘0’ one ‘1’) • H : weak ‘1’ (example: model pull-up resister) • I have never used this value • L : weak ‘0’ 1 1 0 1 Time step 3

  41. Std_logic values • Std_logic values • U : Uninitialized (signal has not been assigned a value yet) • X : Unknow (2 drivers one ‘0’ one ‘1’) • H : weak ‘1’ (example: model pull-up resister) • I have never used this value • L : weak ‘0’ 0 1 1 1 0 X 1 Time step 3

  42. Std_logic values • Std_logic values • U : Uninitialized (signal has not been assigned a value yet) • X : Unknow (2 drivers one ‘0’ one ‘1’) • H : weak ‘1’ (example: model pull-up resister) • I have never used this value • L : weak ‘0’ 0 1 1 1 0 X 1 0 1 Time step 3

  43. Std_logic values • Std_logic values • U : Uninitialized (signal has not been assigned a value yet) • X : Unknow (2 drivers one ‘0’ one ‘1’) • H : weak ‘1’ (example: model pull-up resister) • I have never used this value • L : weak ‘0’ 0 0 1 1 1 X X X 1 Time step 3

  44. Std_logic values • Std_logic values • U : Uninitialized (signal has not been assigned a value yet) • X : Unknow (2 drivers one ‘0’ one ‘1’) • H : weak ‘1’ (example: model pull-up resister) • I have never used this value • L : weak ‘0’ Pull-up resistor ‘1’ Time step 0

  45. Std_logic values • Std_logic values • U : Uninitialized (signal has not been assigned a value yet) • X : Unknow (2 drivers one ‘0’ one ‘1’) • H : weak ‘1’ (example: model pull-up resister) • I have never used this value • L : weak ‘0’ Pull-up resistor ‘1’ 0 U H U Time step 0

  46. Std_logic values • Std_logic values • U : Uninitialized (signal has not been assigned a value yet) • X : Unknow (2 drivers one ‘0’ one ‘1’) • H : weak ‘1’ (example: model pull-up resister) • I have never used this value • L : weak ‘0’ Pull-up resistor ‘1’ 1 0 H 1 Time step 1

  47. Std_logic values • Std_logic values • U : Uninitialized (signal has not been assigned a value yet) • X : Unknow (2 drivers one ‘0’ one ‘1’) • H : weak ‘1’ (example: model pull-up resister) • I have never used this value • L : weak ‘0’ Pull-up resistor ‘1’ Resolution(H,0) = 0 0 1 0 1 Time step 2

  48. Pre-defined VHDL attributes • mysignal’event (mysignal changed value) • mysignal’high (highest value of mysignal’s type) • mysignal’low • Many other attributes • http://www.cs.umbc.edu/help/VHDL/summary.html

  49. Singal vs Varible scope • Signal: global to file • Variable: local to process My_process_1 : process (B,C,Y) Begin A <= B + C; Z <= Y + C; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin X <= Z + 1; Ans <= B + Y; End My_process_2; • VHDL on-line tutorials: • http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html • http://www.cs.umbc.edu/help/VHDL/summary.html • http://www.vhdl-online.de/tutorial/

  50. Singal vs Varible scope • Signal: global to file • Variable: local to process My_process_1 : process (B,C,Y) Begin A <= B + C; varZ <= Y + C; End My_process_1; My_process_2 : process (B,X,Y,Ans1) Begin X <= varZ + 1; Ans <= B + Y; End My_process_2; Each varZ are local to their process. Completely independent • VHDL on-line tutorials: • http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html • http://www.cs.umbc.edu/help/VHDL/summary.html • http://www.vhdl-online.de/tutorial/

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