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Get the total Coverage !

Get the total Coverage !. ID 311C: Utilizing JTAG / boundary scan and JTAG emulation for board and system level test and design verification. GOEPEL Electronics Heiko Ehrenberg Managing Director NA Operations 12 October 2010 Version 1.3. Heiko Ehrenberg.

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Get the total Coverage !

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  1. Get the total Coverage ! ID 311C: Utilizing JTAG / boundary scan and JTAG emulation for board and system level test and design verification GOEPEL Electronics Heiko Ehrenberg Managing Director NA Operations 12 October 2010 Version 1.3

  2. Heiko Ehrenberg • Managing Director of North American Operations at GOEPEL Electronics LLCat Austin, TX • responsible for GOEPEL's operations in the USA, Canada, and Mexico • providing support and consulting services to North American clients • GOEPEL was founded in 1991 and has ~160 employees worldwide, active in JTAG/boundary scan, AOI, AXI, and Functional Test • Prior Experience: • Field Application Engineer for JTAG/boundary scan supporting GOEPEL customers in Germany and then Europe • BSEE from the University of Applied Sciences at Mittweida, Germany

  3. Renesas Technology and Solution Portfolio Microcontrollers& Microprocessors#1 Market shareworldwide * SolutionsforInnovation Analog andPower Devices#1 Market sharein low-voltageMOSFET** ASIC, ASSP& MemoryAdvanced and proven technologies * MCU: 31% revenue basis from Gartner "Semiconductor Applications Worldwide Annual Market Share: Database" 25 March 2010 ** Power MOSFET: 17.1% on unit basis from Marketing Eye 2009 (17.1% on unit basis).

  4. Renesas Technology and Solution Portfolio Microcontrollers& Microprocessors#1 Market shareworldwide * SolutionsforInnovation Analog andPower Devices#1 Market sharein low-voltageMOSFET** ASIC, ASSP& MemoryAdvanced and proven technologies * MCU: 31% revenue basis from Gartner "Semiconductor Applications Worldwide Annual Market Share: Database" 25 March 2010 ** Power MOSFET: 17.1% on unit basis from Marketing Eye 2009 (17.1% on unit basis). 4

  5. Microcontroller and Microprocessor Line-up • Up to 1200 DMIPS, 45, 65 & 90nm process • Video and audio processing on Linux • Server, Industrial & Automotive Superscalar, MMU, Multimedia • Up to 500 DMIPS, 150 & 90nm process • 600uA/MHz, 1.5 uA standby • Medical, Automotive & Industrial High Performance CPU, Low Power • Up to 165 DMIPS, 90nm process • 500uA/MHz, 2.5 uA standby • Ethernet, CAN, USB, Motor Control, TFT Display High Performance CPU, FPU, DSC • Legacy Cores • Next-generation migration to RX R32C H8S H8SX M16C General Purpose Ultra Low Power Embedded Security • Up to 25 DMIPS, 150nm process • 190 uA/MHz, 0.3uA standby • Application-specific integration • Up to 10 DMIPS, 130nm process • 350 uA/MHz, 1uA standby • Capacitive touch • Up to 25 DMIPS, 180, 90nm process • 1mA/MHz, 100uA standby • Crypto engine, Hardware security 5

  6. Microcontroller and Microprocessor Line-up R32C JTAG / boundary scan and JTAG emulation for board and system level test and design verification • Up to 1200 DMIPS, 45, 65 & 90nm process • Video and audio processing on Linux • Server, Industrial & Automotive Superscalar, MMU, Multimedia • Up to 500 DMIPS, 150 & 90nm process • 600uA/MHz, 1.5 uA standby • Medical, Automotive & Industrial High Performance CPU, Low Power • Up to 165 DMIPS, 90nm process • 500uA/MHz, 2.5 uA standby • Ethernet, CAN, USB, Motor Control, TFT Display High Performance CPU, FPU, DSC • Legacy Cores • Next-generation migration to RX H8S H8SX M16C General Purpose Ultra Low Power Embedded Security • Up to 25 DMIPS, 150nm process • 190 uA/MHz, 0.3uA standby • Application-specific integration • Up to 10 DMIPS, 130nm process • 350 uA/MHz, 1uA standby • Capacitive touch • Up to 25 DMIPS, 180, 90nm process • 1mA/MHz, 100uA standby • Crypto engine, Hardware security 7

  7. Innovation Design verification and prototyping Manufacturing test and debug End of line (system) test Field service / warranty/repair On-Chip / In-Circuit Emulation IEEE 1149.x JTAG / boundary scan IEEE 1149.x Functional test IEEE 1149.x (JTAG / boundary scan) +On-Chip Emulation Functional test 8

  8. Intelligent boundary scan solutions GOEPEL is a technology leader in JTAG / boundary scan – creating new, innovative ways to extend the reach of boundary scan beyond pure structural test applications.

  9. Agenda Benefits and limitations of IEEE Std. 1149.1 for board level debug and test Overview of board and system level JTAG/boundary scan applications Utilization of On-Chip Emulation resources for board level connectivity test applications Interlaced JTAG Emulation and boundary scan testing Summary of fault coverage improvements and other benefits

  10. Key Takeaways • By the end of this session you will be able to: • Identify potential board and system level test applications supported by JTAG/boundary scan on specific board/system designs; • Discuss potential test strategies involving JTAG/boundary scan with test engineering / production test groups

  11. JTAG / boundary scan in a nutshell 12 12

  12. Boundary scan test applications TAP Controller TAP Controller Bi-Dir Buffer AND Gates SRAM R Digital CoreLogic Digital CoreLogic /TRST TDI TCK TMS R TDO ID Reg ID Reg /TRST /TRST IR IR TDI TDI TDO TDO BP BP TCK TCK TMS TMS R R

  13. JTAG / boundary scan limitations ... Strictly digital test access (exception: IEEE 1149.4) Quasi-static tests (low I/O toggle rate), limited dynamic test capabilities (exception: BIST) Test access determined by BScan capabilities implemented in devices on the UUT BScan test coverage could be improved: if test points or connector pins are accessed with Tester I/O by accessing analog circuitry with Tester resources by utilizing On-Chip Emulation and Tester resources for dynamic, quasi-functional tests

  14. Boundary scan vs. Emulation Structural Test Efficient ATPG tools Pin Level Diagnostics In-System Test / Programming Flash programming inefficiencies Limits in dynamic test Complexity of cluster tests Need for BScan Register • Functional Test • Fault Coverage • At-Speed Test • FLASH programming speed • µP/µC specific pods • Limited ATPG • Quality of diagnostics • Limited In-System Test / Programming How to get the best of both worlds?

  15. VarioTAP Structural Test Efficient ATPG tools Pin Level Diagnostics In-System Test / Programming Flash programming inefficiencies Limits in dynamic test Complexity of cluster tests Need for BScan Register • Functional Test • Fault Coverage • At-Speed Test • FLASH programming speed • µP/µC specific pods • Limited ATPG • Quality of diagnostics • Limited In-System Test / Programming On-Chip Programming + Interlaced Emulation Test

  16. Classification of boundary scan applications

  17. Utilization of On-Chip Emulation resources for board level connectivity test applications

  18. Generic μP / MCU / CPU model (On-Chip Resources) Emulation Test JTAG Bus IF Type A Flash Analog I/O PCI Express, CAN, LIN, Flexray, BlueTooth, WLAN, USB, LAN, RS232, ... Audio, Video, Legacy analog, Legacy digital, PWM signals, I2C, SPI, μW, ... Core Bus IF Type X Digital I/O Internal Circuits SystemBus IF Mixed I/O On-Board Resources: DRAM, External Periphery, Bridges, etc. Application Type A: Programming Functions for On-Chip or external Flash Application Type B: Bus Control Functions for Bus Emulation Test Application Type C: Test Functions for On-Chip Resources

  19. Flash ISP JTAG PHY JTAG Standard I/I/O Standard I/RAM Standard I/RAM Standard I/I/O Bridge Bus IF Type A Flash Analog I/O I/O RAM PHY Signal Conditioning Standard I/O Standard I/O Core Standard I/O Bus IF Type X Digital I/O Internal Circuits SystemBus IF Mixed I/O TAP JTAG Standard I/FLAS Standard I/FLASH Flash

  20. Bus Emulation Test JTAG TAP JTAG PHY Bus IF Type A Flash Analog I/O Signal Conditioning Core PHY Bus IF Type X Digital I/O Internal Circuits SystemBus IF Mixed I/O TAP JTAG Standard I/O Standard I/FLAS Standard I/RAM Standard I/I/O Standard I/O Bridge Standard I/FLASH Standard I/RAM Standard I/I/O External Tester Channels External Tester Channels Standard I/O Flash RAM I/O

  21. System Emulation Test JTAG TAP JTAG PHY Bus IF Type A FLASH Analog I/O External Tester Channels Signal Conditioning Core PHY External Tester Channels Bus IF Type X Digital I/O Internal Circuits SystemBus IF Mixed I/O TAP JTAG Standard I/O Standard I/FLAS Standard I/RAM Standard I/I/O Standard I/O Bridge Standard I/FLASH Standard I/RAM Standard I/I/O External Tester Channels External Tester Channels Standard I/O FLASH RAM I/O

  22. VarioTAP application development CASLAN Source code Bscan instruction VarioTAP Instruction Bscan Instruction Device Model #1 -- Register descriptions -- Port descriptions -- ……. Device Model #n (µP) -- Register descriptions -- Port descriptions -- … -- VarioTAP Model(s) µP/µC specific models are the key for VarioTAP Access to VarioTAP functions via CASLAN (high-level commands) Device Model #2 -- Register descriptions -- Port descriptions -- ……. -- VarioTAP Model Compiler Executable Selected Device Library SYSTEM CASCON™ Environment Emulation Tool suite for Flash ISP and Testing Available VarioTAP Commands

  23. VarioTAP applications • Test of Digital I/O • Test of Analog / Mixed-Signal I/O • Fast external Flash Programming • On-Chip Flash Programming • Test of Bus Interfaces • Test of Peripheral Circuitry • Dynamic Memory Access Tests • Customer specific Tests • Unique: Interlaced utilization of emulation resources and boundary scan resources

  24. Fault coverage improvements and other benefits • Boundary scan provides: • Embedded test access • Deterministic test coverage • Very good diagnostics • JTAG (on-chip) emulation provides: • Dynamic fault coverage • Verification of circuit functions

  25. Fault coverage improvements and other benefits • VarioTAP combines boundary scan and on-chip emulation to provide: • JTAG controlled functional tests • Interlaced boundary scan and on-chip emulation tests for extended connectivity tests • Automated test generation and deterministic test coverage for (functional) on-chip emulation tests

  26. Questions?

  27. Question 1 Is there a standard defining JTAG / boundary scan resources? If so, which standard? Yes: IEEE 1149.1 Also: IEEE 1149.4, IEEE 1149.6, IEEE 1149.7

  28. Question 2 Name potential board and system level test applications supported by JTAG / boundary scan. Infrastructure test Interconnect test Memory access (cluster) test Logic cluster test In-system programming for Flash, sEEPROM, CPLD …

  29. Question 3 What is one of the most important printed circuit board level “design for test” requirements enabling the utilization of boundary scan capabilities implemented in integrated circuits? Implement a boundary scan chain ! Make the TAP accessible. Allow Compliance enable pattern to be satisfied to enable JTAG / boundary scan compliance.

  30. Feedback Form Please fill out the feedback form! If you do not have one, please raise your hand

  31. Thank You!

  32. For further information, please: Visit our website at www.goepelusa.com Contact your local sales representative Call us at 1-888-4GOEPEL Email us at sales@goepelusa.com Contact information

  33. Appendix

  34. References and tools • White Paper: “Combining Boundary Scan and JTAG Emulation for advanced structural Test and Diagnostics” • Boundary Scan Coach: • software tool demonstrating the key principles of JTAG / boundary scan as defined in IEEE 1149.1 • BSDL Syntax Checker: • software for verification of BSDL syntax and semantics • TAP Checker: • software for validation of JTAG / boundary scan implementations in integrated circuits • CASCON GALAXY: • software for device, board, and system level JTAG / boundary scan test and emulation applications

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