Semiconductor Tracking Detectors – New ( Future ?) Directions

Semiconductor Tracking Detectors – New (Future?) Directions Veljko Radeka, BNL 6th Int’l Hiroshima Symposium, Sept 15,2006 Acknowledgements: Gianluigi De Geronimo, Paul O’Connor, Zheng Li, Pavel Rehak

-- “It is difficult to make predictions …. … particularly about the future”. (A well known 20th century philosopher) -- “It is always wise to look ahead, but difficult to look further than you can see”. -- “The farther backward you can look, the farther forward you are likely to see.” -- “It is a mistake to look too far ahead. Only one link of the chain of destiny can be handled at a time.” -- “I always avoid prophesying beforehand, because it is a much better policy to prophesy after the event has already taken place”. Footnote: “It is a good thing for an uneducated man to read books of quotations”

“History will be kind to us ... … I intend to write it” ( W.C. ~1945)

Scope of the Semiconductor “Tracking Detector” Field • Detector technology: • Si-strips, p+p spray • Si-pixels • Si-3d pixels • MAPS • APS on high rho Si • Hybrid PIN-CMOS • SOI vertically integrated – 3D electronics • CCDs & new developments • APDs & Geiger mode • Materials: Si, Ge, CZT, SiC, Diamond • STJs, STE, bolometers, .. • Research Facility: • LHC + upgrade • RHIC + upgrades • ILC • Numerous light sources (APS, LCLS, NSLS, … • Large telescopes • Space instruments Area of research: • Particle physics • Astro (particle) physics - astronomical observations (350- 1000 nm) - x-ray • Relativistic heavy ion physics • Synchrotron radiation • Electron Microscopy • Biology&Medical Research • Materials science (various x-ray techniques) • Homeland security In DOE BES budget is bigger than HEP! Monolithic Electronics

Electron – (hole, ion) creation energy wi [eV] Application:

Outline 1. Main stream (established!) directions in developments for forthcoming applications (strips and hybrid pixels for LHC, RHIC, …) 2. Examples of some interesting special applications 3. Impact of developments in microelectronics 4. What we would like to see developed in pixel detectors (for light, x-rays and charged particles, ILC, astrophysics)→ Merging of detectors and electronics

1. Developments for LHC and RHIC Ugrades Radiation hardness: - Oxygen and p-spray are here to stay Medium resistvity p material, short strips, thinner substrate, lower noise electronics; 3D electrodes in the vertex; - Silicon will remain material of choice. Materials “damaged to begin with” (GaAs) will remain “materials of the future”. Preferred readout: - single-sided. ac-coupling needed for detector testing. dc-coupling: feedback methods developed to absorb leakage currents dc-coupling (see: G. De Geronimo, ) Vertex in RHIC: MAPS

A1 A2 C t1  z1 t2  z2 Triggers Time Zhong He, et al.: 3-Dimensional Position Sensingin CZT…. Trapping of electrons and material non-uniformity in Z  Depth sensing (EE, z) Pixellated anodes Cathode A1 h+ e- h+ e- C  Z1 C A1   Z2 A2 Single-interaction events: C/A = depth of interaction Multiple-interaction events: Drift-times  individual Zs

Observation of muon tracks Measured Energy deposition Detector: 1.51.51 cm3 CdZnTe Zhong He, et al.: 3-Dimensional Position Sensing in CZT…. • Recognize the type of radiation for background reduction (Internal induced +, - decays, activation -, charged particles) A TPC approach:

Si-pixel detectors in electron microscopy (see also the talk by P. Denes)Multiple scattering of 200keV electrons in 200 mm ofsilicon Rehak et al.

Multiple scattering of 200 keV electrons in 30 mm of silicon Thin detector needed!

Multiple scattering of 200 keV electron in 30 mm Si & 500 mm Be

Avalanche Photodiodes for LSO used in PET (BNL project) Hamamatsu S8550 4x8 array 1.6 x 1.6 mm2 active pixel area CT~ 10 pF Typical G ~ 50 Npe ~ 1200 ~ 60K signal electrons Expected noise in final ASIC ~ 500-600 e’s

The “Roadmap” (1)

The “Roadmap” (2)

Detector Physicist: “Electronics is Cheap!”Cost per transistor: But …

… supply and threshold voltages have not followed the scaling … Proc. IEEE

DVT Threshold mismatch due to discrete dopant distribution 3D p-MOSFET simulation with stochastically placed dopants D.J. Frank, IBM J. Res. Dev. 46, 235-244, Mar./May 2002

fT vs power Bandwidth for low power analog is not as high as the advanced technology might indicate

gm/gds Gain gm/gds degraded in ultra-scaled devices: • Speed/intrinsic gain tradeoff • fT ~ 1/LG for min-LG devices • Output conductance gds sensitive to geometry and bias • Gain gm/gds degraded in ultra-scaled devices: • failure to adhere to classical constant-E scaling

The low supply voltage headroom in scaled CMOS processes imposes limits on analog circuit topologies. The increasing ratio of VTH/VDD rules out the use of many classical analog design topologies. The cascode connection, useful in providing high gain loads and current sources, becomes dificult once VDD falls below ~1.2V. CMOS transmission gates, commonly found in sample/hold and switched capacitor circuits, perform poorly in scaled processes as the control gate voltage is limited and self-discharge rates increase. Source followers limit the available signal swing and have to be avoided in output stages and other large-signal circuit blocks. Analog design becomes more difficult with scaling of CMOS P. O’Connor, SNIC 2006

Gate tunneling current • Gate current expected to increase 100 – 200 x per generation below 0.18 mm • Jox ~ 100 A/cm2 projected for Lmin = 0.1 mm generation with nitrided SiO2 • Considered tolerable for digital circuits (total gate area per chip ~ 0.1 cm2) • Typical input FET would have IG ~ 1 nA at 1 µsec for 130 nm; ENCp , increasing exponentially with scaling SiO2 gate leakage current (Lo et al., Electron Dev. Letters 1997)

Active and Passive Power Density vs Gate Length IBM J. Res. Dev.

What at the end of the Roadmap?Stages of nanoscale devices future development:http://www.research.ibm.com/journal/rd/, Sept. 2006 Performance enhancement by 1d and 2d carrier confinement, Carbon nanotube (CNT) FETs ------------------ Distant future: new devices such as spin transistors – different architecture IBM J. Res. Dev.

Single electron and single molecule transistors(1) single electron transistors (first introduced By K. Likharev in 1985) Tunnel junctions Quantum dot Coulomb blockade: 1 e on 1 aF ~ 160 mV Electrometer noise: ~ 10-5 e rms/Hz1/2 ~1 aF (kTC)1/2~ 0.4 e rms at 300K

Single Molecule (Electromechanical) Transistor:(studies of carbon nanotubes) C. Joachim, Proc. IEEE,86(1998)184

Bell LabsDec. 1947

The use of single electron transistors in particle and photon detectors is somewhat beyond the horizon….However, if the detectors ever get to nanoscale voxels, and less than ~ 10 atofarads, then…(we are now at a few femtofarads)

Toward merging of detectors and electronics … Goal: Detector thickness optimized to application (from ~30μ to ~2mm), with all appropriate readout functions, different in each case Developments in CCDs for astronomy, x-ray and particle physics PIN-CMOS bump bonded hybrids Single transistors on high resistivity silicon MAPS for ILC Bonding of low resistivity silicon (CMOS) to high resistivity silicon detector; single layer or multilayer (3D) electronics

CCDs - Partial vs Full Depletion • Conventional CCDs 15-20 µm thick on 20-100 ohmcm silicon cannot be fully depleted with 15-20 volts. PSF (rms) ~ thickness of undepleted region (≥~6-7 µm) • Full depletion essential for minimal charge spreading, PSF (rms) < ~ 4 µm • Methods to ensure full depletion: • High-resistivity substrate >5 kohm cm • Bias on p+ (n+) back-surface(30-50 volts on 100 µm) Illustration from: Barry Burke Fully depleted thick CCDs pioneered by S. Holland, LBNL

E ~ 3kV/cm 5-10 nm p N~1012/cm-2 ~ 5-10 kohmcm p++ N~1019/cm3 Critical technology issues for thick overdepleted sensors for astronomy: 1. 3d-layout, doping&biasing of p+ and n+ regions, guard ring design to allow independent biasing of the (back side) sensor window. 2. Conductive (ohmic) window to allow independent biasing, and not absorb near-UV. CCD view across the buried channel and the channel stops. The potentials among the channel, the channel stops and the window must be arranged so that the conduction path between the window and the channel stops is pinched-off , i.e., that the field lines from the window reach the buried channel and not the channel stops A 3-phase CCD shown schematically along the charge transfer direction. A p-channel (n-substrate) device is indicated. The readout node capacitance is typically 15 to 30fF, corresponding to a conversion gain of between ~10 and ~5 microvolts/electron respectively. An illustration of the termination of electric field at the window of an overdepleted sensor. A highly doped layer at the window is required to bring the electric field to zero before it can reach the surface, and to leave a thin (a few nm) conductive layer at the surface. V. Radeka, SNIC 2006

Multi-port 4K x 4K = 16M CCD Column Parallel Readout Blooming column length 2000 pixels 2 contiguous imaging areas 2kx4k separated by a blooming stop less than 1-2 pixel rows wide Readout segment boundary (no discontinuity) Dog-leg output: (R. Bredthauer, STA) 500x 2000

Readout Noise in CCDs Lincoln Labs Sense-node capacitance~5 fF (20 µV/e-) 10e 15fF 1 MHz Source Follower transistor: Channel length L: Channel width W: Power: By CCD process: ~4-6 μm ~45 μm 5-10 mW MOS(P): ~0.4-0.5 μm ~10 μm <100 μW CMM For equal noise! Results From: Burke, Jorden, Vu, SDW Taormina 2005

Short Column 2-phase CCD (SCCCD) M. Breidenbach, Presentation at this Symposium Bunch 1 2 3 4 5 6 Time Amplitude 15 8 18 5 14 5 17 18 3 8 7 16 CCD Clock 12 15 11 10 9 6 4 2 1 13 • Utilizes CCD correlation of position with bunch twice to “solve” for position and bunch time. • Clock CCD at ~10 MHz • Use LHC style bump bonding for connections. • Occupancy of a short column/column read time ~0.5 (inner layer) • Once the bunch is identified, then ~no ambiguity for position.

PIN-CMOS • Independent optimization of the PIN and CMOS design and processing • Electronic shutter by reset transistors • Blooming control • Large dynamic range by readout “up the ramp”; addressable guider readout • Lower power dissipation, low voltage for CMOS • Fixed pattern noise • pixel-to-pixel (stable) gain differences due to amplifier per pixel • capacitive (deterministic) crosstalk to adjacent pixels • CDS over longer time intervals J. Beletic. Et al.:

Indium Bump Bonds (samples, ATLAS, CMS) H. Krueger, NIM A 551(2005)1

Indium Bump Bonding Bond yield by RVS and RSC >0.999 Indium interconnect array on 8 um centers compared to a human hair. From: K.T. Veeder et al., “Enabling Technologies for Large Hybrid Focal Plane Arrays with Small Pixels”, Raytheon Vision Systems

Potential distribution: +15V source top gate drain clear bulk 0V 0V internal Gate n+ p+ p+ n+ n+ ~1µm 1 mm - - p - - + s n - i x internal gate a - y - - 50 µm r - - - t e - + m m - 50 µm - 300 mm y s + - n + - p+ rear contact [TeSCA-Simulation] The DEPFET Principle (from N. Wermes) • p-channel JFET or MOSFET integrated on high-ohmic n-substrate, sidewards-depleted (as in drift det., Gatti, Rehak, 1983). • electrons arecollected in an internal gate close to the surface • the device can be switched on/off by an external (top) gate • CLEAR complete ? • low noise (no N, no kT/C ) • fast pedestal subtraction J. Kemmer und G. Lutz;, NIM A253 (1987) 365

“JFET switch on high rho (~10 kohm cm) Si”: X-ray passive matrix pixel P. Rehak, et al.

S S Row D G D Passivation CVD / SOG CVD / SOG S S G G BPSG BPSG BPSG BPSG Column FOX FOX S S 500µm MOSFET on high rho Si (IBM process) • Circularly symmetric MOSFET replaces similar JFET in the previous design • Thin gate (5nm) oxide is rad-hard • Circular symmetry is automatically 'enclosed gate' design 3µm 7µm • n-type • n+ implant • p+ implant • SiO2 • Weak p • Metal 1 • Metal 2 • Polysilicon 3µm 7µm Collaboration: P. Siddons et al.

Monolithic Active Pixel Sensor (MAPS) • Fabricated on standard CMOS silicon wafer • Charge produced in p- epitaxial layer diffuses to active junction • Thin active layer (2 – 10 mm), low signal • Diffusive charge collection  long collection times, large lateral spread • Charge removed by reset transistor • In-pixel electronics limited to one transistor type • Chip size limited VDD RE_SEL ROW_SEL metal COLUMN LINE n+ Deptuch, et al; Kleinfelder, et al.,; ……………………. ………………………. nwell pwell photo diode poly diffusion isochron

Marty B. (this Symposium): “Bunch identification (probably) requires all pixels to be continuously sensitive throughout the train. So ~1x109 front end amplifiers must be on for 1 ms. Unlikely that the current in each amplifier will be less than 1 μAmp So vertex detector needs ~1000 ampere supply” MAPS for ILC? Gianluigi De Geronimo, BNL: Amplifier before the comparator needed due to small signal from the thin epi layer: Gain: 8 in <100ns VDD= 1.4 V I= 200 nA ENC~ 40 e rms Including the comparator, the current is expected to be ¼ to 1/3 of Marty’s assumption.

Trends: • High performance (“scientific”) CCDs ~75-200 μm thick for astronomy (more for x-rays) – -being developed by several manufacturers. • Column parallel conventional CCD readout (transistor on the chip) will be limited to a small number of segments (power dissipation, number of connections). • Silicon PIN CMOS bump bonded hybrids remain to be proven and accepted in astronomy. If so, will prevail for short integration/readout times. CCDs will still be best for long integration times. • CCD-CMOS hybrids need to be explored for high performance imaging in astronomy (they are being actively developed for other fields). No extreme CCD flatness and thin window requirements for particle physics.

Information: -- R. Jarema, Perugia 2006 FEE -- A. Klumpp, et al., - “ – -- R. Lipton, this Symposium First significant goal: bonding of 1 layer of fully functional CMOS with high rho Si: -- 50 microns would improve the MAPS. -- 0.5 to 2 mm will benefit various x-ray detectors. … then 3D with optimized analog and digital functions Bonding of low resistivity silicon (CMOS) to high resistivity silicon detector; single layer or multilayer (3D) electronics

Semiconductor Tracking Detectors – New ( Future ?) Directions