ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems

1. ECE 697B (667)Spring 2006Synthesis and Verificationof Digital Systems Verification Combinational Equivalence Checking ECE 667 - Synthesis & Verification - L24

2. Out In CL PI Po CL Ps Ns R Equivalence Checking • Two circuits are functionally equivalent if they exhibit the same behavior • Combinational circuits • for all possible input values • Sequential circuits • for all possible input sequences ECE 667 - Synthesis & Verification - L24

3. Architectural Specification (informal) Layout Implementation (GDS II) Circuit Implementation (Schematic) RTL Specification (Verilog, VHDL) Test Programs Cycle Simulation Equivalence Checking Circuit Simulation Application of EC in mP Designs ECE 667 - Synthesis & Verification - L24

4. Engineering Changes (ECOs) Standard Cell Implementation Final Implementation RTL Specification Cell-Based Synthesis Equivalence Checking Equivalence Checking Application of EC in ASIC Designs ECE 667 - Synthesis & Verification - L24

5. Combinational Equivalence Checking • Functional Approach • transform output functions of combinational circuits into a unique (canonical) representation • two circuits are equivalent if their representations are identical • efficient canonical representation: BDD • Structural • identify structurally similar internal points • prove internal points (cut-points) equivalent • find implications ECE 667 - Synthesis & Verification - L24

6. Functional Equivalence • Circuits for which BDD can be constructed • represent multi-output circuits as shared BDDs • BDDs must be identical (for the same variable ordering) • Circuits whose BDDs are too large • cannot construct BDDs, memory problem • use partitioned BDD method • decompose circuit into smaller pieces, each as BDD • check equivalence of internal points (cut-point method) ECE 667 - Synthesis & Verification - L24

7. Degree of Structural Difference Structure- independent techniques Combined methods Structure-dependent techniques Size EC Methods • Structure-independent techniques: • exhaustive simulation • decision diagrams (*DD*) • Structure dependent techniques: • graph hashing • SAT solvers including learning techniques ECE 667 - Synthesis & Verification - L24

8. F G f2 g2 z z f1 g1 y y x x Functional (Structure-independent) Methods • Decompose each function into functional blocks • represent each block as a BDD (partitionedBDD method) • define cut-points (z) • verify equivalence of blocks at cut-points starting at primary inputs ECE 667 - Synthesis & Verification - L24

9. v1 f1 f1 f3 f3 f2 f2 v2 v2 0? x 0? 0? v1 Cutpoint-based EC Cutpoints are used to partition the Miter • Cutpoint guessing: • Compute net signature with random simulator • Sort signatures + select cutpoints • Iteratively verify and refine cutpoints • Verify outputs ECE 667 - Synthesis & Verification - L24

10. F G f2 g2 z1 z2 f1 g1 y y x x Cut-Points Resolution Problem • If all pairs of cut-points (z1,z2) are equivalent • so are the two functions, F,G • If intermediate functions (f2,g2) are not equivalent • the functions (F,G) may still be equivalent • this is called false negative • Why do we have false negative ? • functions are represented in terms of intermediate variables • to prove/disprove equivalence must represent the functions in terms of primary inputs (BDD composition) ECE 667 - Synthesis & Verification - L24

11. F G f2 g2 z z f1 g1 y y x x Cut-Point Resolution – Theory • Let f1(x)=g1(x) x • if f2(z,y)  g2(z,y), z,y then f2(f1(x),y)  g2(f1(x),y)  F  G • if f2(z,y)  g2(z,y), z,y  f2(f1(x),y)  g2(f1(x),y)  F  G We cannot say ifF  G or not • False negative • two functions are equivalent, but the verification algorithm declares them as different. ECE 667 - Synthesis & Verification - L24

12. 0, F  G (false negative) 1, F  G (true negative) F G Cut-Point Resolution – cont’d • How to verify if negative is false or true ? • Procedure 1: create a miter (XOR) between two potentially equivalent nodes/functions • perform ATPG test for stuck-at 0 • find test pattern to prove F  G • efiicient for true negative (gives test vector, a proof) • inefficient when there is no test ECE 667 - Synthesis & Verification - L24

13. , F  G (false negative) Non-empty, F  G G F F G =  = Cut-Point Resolution – cont’d • Procedure 2: create a BDD for F G • perform satisfiability analysis (SAT) of the BDD • if BDD for FG = , problem is not satisfiable, false negative • BDD for FG, problem is satisfiable, true negative Note: must compose BDDs until they are equivalent, or expressed in terms of primary inputs • the SAT solution, if exists, provides a test vector (proof of non-equivalence) – as in ATPG • unlike the ATPG technique, it is effective for false negative (the BDD is empty!) ECE 667 - Synthesis & Verification - L24

14. d1 d2 a F G • a • b b c Structural Equivalence Check • Given two circuits, each with its own structure • identify “similar” internal points, cut sets • exploit internal equivalences • False negative problem may arise • F  G, but differ structurally (different local support) • verification algorithm declares F,G as different • Solution: use BDD-based or ATPG-based methods to resolve the problem. Also: implication, learning techniques. ECE 667 - Synthesis & Verification - L24

15. d=x b=x f=1 a=0 d=0 b=x f=0 c=x e=x a=1 c=x e=0 Implication Techniques • Techniques that extract and exploit internal correspondences to speed up verification • Implications – direct and indirect Direct: a=1  f=0 Indirect (learning): f=1  a=0 ECE 667 - Synthesis & Verification - L24

16. G H a a a H b b b G=1 c 0 1 0 1 Learning Techniques • Learning • process of deriving indirect implications • Recursive learning • recursively analyzes effects of each justification • Functional learning • uses BDDs to learn indirect implications G=1  H=0 ECE 667 - Synthesis & Verification - L24

17. a H b G=1 c Learning Techniques –cont’d • Other methods to check implications G=1  H=0 • Build a BDD for G • H’ • If this function is satisfiable, the implication holds and gives a test vector • Otherwise it does not hold • Since G=1  H=0  (G’+H’)=1, build a BDD for (G’+H’) • The implication holds if (G’+H’)=1 (tautology) ECE 667 - Synthesis & Verification - L24

18. Summary • Industrial EC checkers almost exclusively use a combinational EC paradigm • sequential EC is too complex, can only be applied to design with a few hundred state bits • combinational methods scale linearly with the design size for a given fixed size and “functional complexity” of the individual cones • Still, pure BDDs and plain SAT solvers cannot handle all logic cones • BDDs can be built for about 80% of the cones of high-speed designs • less for complex ASICs • plain SAT blows up on a “Miter” structure • Contemporary method highly exploit structural similarity of designs to be compared ECE 667 - Synthesis & Verification - L24