Agenda

1. Agenda • Design Flow • Circuit Design • Process Design • What is semi custom design? • Example • Device physics

2. Circuit Design Flow • Receive/develop logic, power, timing, area specification (gain, bandwidth ) • Get logic working in verilog or vhdl • Size transistors by hand • Verify in schematic spice adjust W/L appropriately • Layout and re-verify all specifications • Fabricate • Test

3. Process Design Flow • Determine rough thickness of oxides and junction depth pick process and supply Voltages and VT • Use hand calculations to pick doping levels • verify that the oxide will be thick enough for the voltage range • Xj does not violate Break down rules • Design Process with athena cad tool • Verify the process in silicon • Develop tech file so a design can use your process • spice deck, DRC LVS checks, VT ,RS • Keep process under control

4. Sample Layout Design Rules • Make sure that we have a high yield on our fabrication process. • How many transistors meet specification out of how many we made. • This need to be as close to one as possible. • If there is no duplication of functionality one bad transistor can make a 10 million transistor CPU fail! • Low yields force you to test more of your circuits. • Testing represents a significant amount of the fabrication costs

5. Alignment Errors We need to have a minimum overlap of the metal to contact to take into account the inherent errors in alignment. • A- No Errors • B- Worst Case x misalignment • C- Worst Case y misalignment • D- Worst case x and y

6. Minimum Feature Size • The smallest • gate length we can manufacture reliably • Depends on PL and Etch • smallest diffusion region • Depends on PL and Etch • minimum separation of diffused regions • Depends on how far junctions diffuse during processing • minimum separation of metal lines • Depends on PL, Etch and electrical characteristics • minimum contact width • Depends on Etch, PL and contact resistance

7. Design Rules for Our NMOS Process • For high yields we need to have a process that can withstand large process variations • ½ of our smallest feature size is equal to l. • l is equal to 8 mm

8. Design Rules for Our NMOS Process

9. Transistor

10. Resistor

11. Alignment Rules • Source/Drain Resistors- First Mask • Thin oxide mask- Align to level 1 • Contact window mask- Align to level 1 • Metal mask- Align to level 2

13. Review • Oxide Thickness • For Field oxide solve for minimum thickness to achieve a large VT • Choose a growth method and temperature and solve for time • For Gate Oxide solve for an oxide thickness to achieve a VT of around a volt • Choose a growth method (wet or dry) and growth temp and solve for time

14. Review • Diffusion • Pick a sheet resistance • Pick a junction depth, and temp, solve for time • (for now assume that the sheet resistivity will be correct)

15. Review • Process • Field oxide • S/D Diffusion • Gate oxide • Contact • Metalization

16. Electrical Calculations

17. Electrical Calculations

18. Semi Custom IC design • The most expensive and time consuming layers are pre-processed • S/D diffusion, Gate oxide, contact, and metalization • Circuits are made by wiring together the pre laid out transistors. • One mask is made and PL done on wafers. • Since the wafers are predone the turn around time is very short. • Since the transistors are pre laid out design time is reduced!

19. Resistor Pass-through

20. MOSFET

21. Blank Logic Cell Schematic

22. Blank Logic Cell Layout Metal1 and S/D diffusion are connected by the contact layer, otherwise they pass over each other. Metal1 crossing a Metal1is a short as is a S/D cross. Green –S/D Diffusion Red –Gate Oxide Orange –Contact Blue –Metal1

23. INV Schematic

24. INV Layout

25. NAND3 Schematic

26. NAND3 Layout

27. NOR3 Schematic

28. NOR3 Layout

29. Cells Snap Together

30. AND3 Layout

31. Can you do a two input mux?

32. Modeling the MOSFET

33. VT0

34. VT short channel

35. VT • VT changes with VSB This will cause trouble later.

36. Mobility • Mobility changes with electric field • The constant KNP, is never constant • We use an average

37. l • This is due to the channel length narrowing. • The reversed biased diode’s depletion region gets bigger with VDS, and thus the length of the channel gets smaller, and thus the ID goes up.

38. What does the circuit design engineer control? • How big W and L are. • How the wires are connected. • This does not sound like much is it is a lot.

39. What does the process design engineer control? • Tox • Na • Junction Depth • Qi (kind of)

40. What doe we have to do? • We need to finalize the process so we have reasonable VT, l, g and KNP values. • We really need a positive threshold VT. • Gate oxide experiments. • Try and find out l, g and KNP from the current process so we can finalize mask design. (testing) • Finalize mask design.

41. What doe we have to do? • Verify design environment (drc, lvs etc.) • Verify logic cell • Develop analog leaf cell • Think about cool things we can put on the mask. • Develop Cox, Rs test structures.

42. What do we have to do? • Learn fabrication equipment • Learn test equipment • Develop automated l, g and KNP extraction routines. • Develop Athena run deck to match process • Write Traveler linked to run deck