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Power Delivery Network Optimization for Low Power SoC

Power Delivery Network Optimization for Low Power SoC. Anil Gundurao Melinda Yang Eileen You Harpreet Gill System LSI SoC Bay Area R&D Samsung Semiconductor Inc. SoC Power Integrity Challenges. PCB. Package. VRM. Die. Decap. Decaps. 28nm SoC flip chip package

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Power Delivery Network Optimization for Low Power SoC

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  1. Power Delivery Network Optimization for Low Power SoC Anil Gundurao Melinda Yang Eileen You Harpreet Gill System LSI SoC Bay Area R&D Samsung Semiconductor Inc.

  2. SoC Power Integrity Challenges PCB Package VRM Die Decap Decaps • 28nm SoC flip chip package • 10M+ instances, 500+ macros • 3 operating voltages • 50+ clock domains • Complexity of simulating PDN • SoC complexity: Size, Modes/corners, voltage domains • System complexity: Board and Package • Early analysis and optimizations • Model, Analyze and Optimize • System PI analysis • Add more detailed models in phases

  3. Power Delivery Network Model Pkg Decap

  4. Generatingchip model Operating freq • Estimate chip impedance • Intrinsic and Intentional decap • Estimate Rdie / Cdie at operating frequencies

  5. Z11 Plots Comparison Lpkg Cdie BoardLC Impedance BoardR Decap Self-resonance Frequency Board + Pkg (embedded decap) + Die Board + Pkg (substrate only) + Die Die + Pkg(with embedded decap) Die + Pkg (Substrate only) • Adding board model changes the Z11 plots • Impact on time-domain noise depends on freq content

  6. Understanding Current Signature Mode 1 Mode 2 FFT up to 500MHz • Demand current = f (circuit switching activity) • FFT (current) Energy concentrated > 500MHz FFT up to 3GHz Energy concentrated at harmonics of 50MHz

  7. Optimization: Impact of PDN components • Adding on-chip decaps • Changing Package model • Adding embedded decaps • Updating board Model Voltage at Pads -- Board + Pkg (embed decap) -- Pkg (no decap) -- Board+ Pkg (no decap) -- Pkg (embed decap) Sim Time

  8. Impact of On-chip Decap on DvD No Decap With Decap VCD1 VCD2

  9. On-Chip Decap & Package Core Thickness Impact

  10. Impact of Package and Board impedance Including Board impedance impacts DvD results Having Package/ Board decaps will also impact DvD

  11. Summary Detailed DVD Database System PI Model Compare • For Power Integrity verification: • Critical to model all components of the system PDN • Time-domain and Frequency domain analysis • Model the system early • Estimated and lumped models to predict the PDN response • Use the system model to study effects of different PDN parameters.

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