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Hardware accelerator for Efficient error-correcting codes

Hardware accelerator for Efficient error-correcting codes. Christine Kuhlman Northern Arizona University Mentor: Dr. Elizabeth Brauer. Intro. Why is this important? Static noise is an annoyance Error-Correcting Codes can correct for noise ECC Evaluation of ECCs requires millions of cases

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Hardware accelerator for Efficient error-correcting codes

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  1. Hardware accelerator for Efficient error-correcting codes Christine Kuhlman Northern Arizona University Mentor: Dr. Elizabeth Brauer

  2. Intro • Why is this important? • Static noise is an annoyance • Error-Correcting Codes can correct for noise • ECC • Evaluation of ECCs requires millions of cases • Software testing is too slow • C++ and MATLAB • Hardware accelerator Transmitter Noise Receiver

  3. Objectives • Gather Statistics • Display Statistics • Optimize Field Programmable Gate Array Speed • FPGA • Implement Realistic Code

  4. Hardware Accelerator • Gaussian Noise Generator • GNG • Low-Density Parity-Check • LDPC Transmitter “0000” GNG Receiver “0010” LDPC

  5. Data • Taken using Cyclone II • Programmed in VHSIC Hardware Design Language • VHDL • FPGA implemented

  6. Analysis • FPGA vs. VHDL • FPGA vs. C++ or MATLAB

  7. Conclusion • Most important part • Functional hardware accelerator with a realistic code • Future work • Even more complex codes • Add LDPC • Tool to evaluate ECC

  8. Acknowledgements • NASA Space Grant • Dr. Elizabeth Brauer – Mentor • Dr. Sheryl Howard • Mike Thomson

  9. References [1] D Lee, W Luk, J D. Villasenor, and P.Y.K. Cheung, “A Gaussian Noise Generator for Hardware-Based Simulations,” IEEE Transactions on Computers, vol. 53, no. 12, pp. 1523-1534, Dec. 2004. [2] DE2 Development and Education Board. <http://www.altera.com/education/univ/materials/boards/uni-de2-board.html>, 22 Feb. 2009

  10. Any Questions?

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