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Ontogenetic hardware

Ontogenetic hardware. Ok, so the Tom Thumb algorithm can self-replicate an arbitrary structure within an FPGA But what kind of structures is it interesting to self-replicate. Ontogenetic hardware. Embryonics = embryonic electronics:

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Ontogenetic hardware

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  1. Ontogenetic hardware • Ok, so the Tom Thumb algorithm can self-replicate an arbitrary structure within an FPGA • But what kindof structures is it interesting to self-replicate

  2. Ontogenetic hardware Embryonics = embryonic electronics: Drawing inspiration from growth processes of living organisms to design complex computing systems Phylogeny (P) [Evolvability] PO hw PE hw POE hw Ontogeny (O) [Scalability] OE hw Epigenesis (E) [Adaptability]

  3. Bio-Inspired Approaches • Growth • Self-organization • Massive parallelism (multicellular systems) • Issues that growth can potentially address: • Complexity • Scalability • Fault tolerance

  4. Caenorhabditis Elegans 11 December 1998

  5. Caenorhabditis Elegans From S.F. Gilbert, Developmental Biology, Sinauer, 1991

  6. Multicellular Organization 959 somatic cells

  7. Cellular Differentiation Pharynx Intestine

  8. Embryonics: How? Iterative electronic circuit based on 3 features: • multicellular organization • cellular division • cellular differentiation

  9. Embryonics Landscape Population level S (population = organisms) Organismic level S (organism = cells) Cellular level S (cell = molecules) Molecular level (basic FPGA's element)

  10. StopWatch

  11. StopWatch

  12. Multicellular Organization

  13. StopWatch

  14. StopWatch • First step: design of a totipotent cell (stem cell) (of course, in practice it can be optimized)

  15. StopWatch

  16. Cellular Differentiation

  17. Cloning

  18. Cloning

  19. Self-Repair

  20. BioWatch • The application can of course be anything… • But then, the size and structure of the cell will vary from application to application: we need programmable logic!

  21. MUXTREE Molecule • The “molecular” layer of Embryonics is an FPGA

  22. Cellular Self-Replication • But if we use FPGAs, then we need to CREATE the array of cells in the first place, before differentiation can take place (self-replication)

  23. Cellular Self-Replication • But if we use FPGAs, then we need to CREATE the array of cells in the first place, before differentiation can take place (self-replication)

  24. Cellular Self-Replication • But if we use FPGAs, then we need to CREATE the array of cells in the first place, before differentiation can take place (self-replication)

  25. Cellular Self-Replication • Self-replication will allow the same FPGA partial configuration to be duplicated as many times as needed

  26. Cellular Self-Repair • But self-replication, and custom FPGAs, can ALSO be used to improve the reliability of the system

  27. Cellular Self-Repair • But self-replication, and custom FPGAs, can ALSO be used to improve the reliability of the system … within limits

  28. Operation of the Cell

  29. Kill a Molecule

  30. Recovered Molecule

  31. Kill Again (Kill a Cell)

  32. Recovered Cell

  33. Implementation - The BioWall

  34. Genotype Layer • Phenotype Layer • Mapping Layer Example – Automatic Synthesis Application-specific (parallel) functions Developmental algorithm Genetic code

  35. Example – Automatic Synthesis Totipotent Cell • Phenotype Layer • Mapping Layer • Genotype Layer

  36. Example – Automatic Synthesis Programmable Logic Totipotent Cell

  37. Example – Automatic Synthesis Programmable Logic Cellular Array

  38. What kind of applications can take advantage of this kind of system? Complex "real-world" streaming applications computation is carried out sequentially can be represented by a DAG of computation nodes each node processes data locally then forwards them to the next node in the graph Applications × ×+ ÷≠ FFT + DCT IN OUT

  39. READ DCT QNTZ CMPR WRT Example: JPEG • Specialized MOVE functional units can be designed for each of these steps IN OUT

  40. Context Programmable substrate × ×+ ÷≠ FFT + DCT IN OUT Problem: task or resource allocation – i.e. how do we map the graph nodes to the array? Specifically: dynamic allocation

  41. Self-Scaling Stream Processing Source Funct B Funct A Funct A Funct C Funct C Join Funct A Funct A Funct C Funct C Funct A Funct A Funct A

  42. SSSP The MJPEG application consists of a four-stage computation pipeline. The data to be compressed are composed of 192 bytes corresponding to an 8x8 array of pixels using 24-bit colour. The maximum rate achievable (determined by the input rate) is of 700 packets per second - roughly 1 MBit/second. With a single pipeline, the performance tops at about 60 packets per second.

  43. SSSP When performance peaks, the average output rate is of 675 packets per second (out of a maximum of 700): this technique allows to multiply the throughput by a factor of 11 using 28 processors.

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