State Machines Timing Computer Bus Computer Performance Instruction Set Architectures

1. State Machines Timing Computer Bus Computer Performance Instruction Set Architectures RISC / CISC Machines

2. 4 1 8 4 30 25 5 20 10 15 Combinational vs. Sequential Logic • There are two types of “combination” locks Combinational: Success depends only onthevalues, not the order in which they are set. Sequential: Success depends onthesequenceof values (e.g, R-13, L-22, R-3). A Computer is an example of a Sequential Circuit

3. Information Storage:D Flip Flop (D Latch) D | Qn+1 0 | 0 1 | 1

4. Register • A register stores a multi-bit (vector) value. • We use a collection of D-latches, all controlled by a common write enable pulse, call it WE. • When the write enable WE=1, the n-bit value D is written to register.

5. Timing Diagram Conventions

6. 4 1 8 4 30 25 5 20 10 15 Back to our Sequential Logic This one. Combinational: Success depends only onthevalues, not the order in which they are set. Sequential: Success depends onthesequenceof values (e.g, R-13, L-22, R-3).

7. A Finite State Machine • Combinational logic • Determine outputs at each state. • Determine next state. • Storage elements • Maintain state representation. State Machine Inputs Outputs Combinational Logic Circuit Storage Elements Clock

8. The Clock • Frequently, a clock circuit triggers transition fromone state to the next. • At the beginning of each clock cycle, the state machine makes a transition, based on the current state and the external inputs (Synchronous). • Not always required. In lock example, the input itself triggers a transition (Asynchronous). “1” “0” One Cycle time

9. State • The state of a system is a snapshot of all the relevant elements of the system at the moment the snapshot is taken.

10. Finite State Machine • A description of a system with the following components: • A finite number of states • A finite number of external inputs • A finite number of external outputs • An explicit specification of all state transitions • An explicit specification of what determines each external output value • Often described by a state diagram: - The set of all possible states. - Inputs that trigger state transitions. - Outputs associated with each state (or with each transition).

11. State of Sequential Lock Our lock example has four different states, labelled A-D:A: The lock isnot open,and no relevant operations have been performed. B: The lock isnot open,and the user has completed the R-13 operation. C: The lock isnot open,and the user has completedR-13, followed by L-22. D: The lock isopen.

12. State Diagram • Showsstates (e.g. A) andactions (e.g. R-13) that cause atransitionbetween states.

13. Another Example of a State Machine Repeat Forever: • Fetch Instruction • Fetch Operand(s) • Execute Operation • Store Result • Check for Interrupt

14. Computer Bus Buses are composed of three sets of lines Not all devices will use all lines in each category

15. Synchronous Timing Diagram

16. Asynchronous Timing – Read Diagram

17. Asynchronous Timing – Write Diagram

18. Assessing Computer Performance • Clock Speed ? • Response time ? • Throughput ? • Response Time or Throughput for what type of application(s) ? • Power Consumed ? • Cost ? • Reliability ? • Ease of Use ? • Applications Supported ? • Portability ? • Access ? • ?

19. Instruction Set Architectures What impacts a machine language instruction format ? • Operation codes • Number of Operands (Source and Destination) • Address Modes • Address Range • Address Granularity (Byte, Word, etc) • Number of Registers (and Register Sets) • Types of Processing (String, integer, FP, Arrays,..) • Machine Word Length • Variability of Instruction Length • Context Switching Support • Stack Support • Interrupt Support • Operating System Support • Applications (Computation, Control, Embedded System, Data base, • HLL Languages Supported • Hierarchy of “Versions” • Speed Requirements • I/O Support • Instruction mix

20. Number of Operands • 3 Operands • 2 Operands • 1 Operand • 0 Operands

21. Addressing modes • Immediate • Direct • Indirect • Relative • Register Indirect • Displacement (Base-Register, Indexing, Pre/Post indexed) • Stack

22. Designing an ISA • 8 Bit words • 16 Bit words • 32 Bit words • Multiple words

23. CPU Hardware What might be added ? • Register Sets • Stack • Longer Instruction Register • Address Registers • Context Switch Registers • Cache • Partition Pointer Registers

24. Some Classes of Today’s Computer Architectures • CISC – Complex Instruction Set Computer • RISC – Reduced Instruction Set Computer • Superscalar – Multiple similar processing units are used to execute instructions in parallel • Multicore – Multiple Processors executing instruction in a complementary way

25. Driving force for CISC • Software costs far exceed hardware costs • Increasingly complex high level languages • A “Semantic” gap between HLL & ML • Word size was increasing. • This Leads to: • Large instruction sets • More addressing modes • Hardware implementations of HLL statements

26. Intention of CISC • Ease compiler writing • Improve execution efficiency • Support more complex HLLs

27. RISC Key features: • Large number of general purpose registers (or use of compiler technology to optimize register use) • Limited and simple instruction set • Emphasis on optimising the instruction pipeline & memory management, i.e. leverage newer hardware complexitiesnow potentially available.

28. RISC Characteristics • A Single Instruction size, typically 4 bytes • A small number of data addressing modes, typically less than 5 • No indirect Addressing that requires two memory accesses • No operations that combine load/store with arithmetic • No more than one memory addressed operand per instruction • No arbitrary data alignment for load/store operations • Large number of instruction bits for integer register addressing, typically at least 5 • Large number of instruction bits for FP register addressing, typically at least 4

29. Which is better? • Is the execution of large special purpose instructions more efficient than execution of many simple instructions ? • Which programs are really “shorter” ? • Which are really faster ? • What is the impact of having to support many languages? • What are the legacy challenges ? • What are the cost tradeoffs ? • Can compilers be better made to exploit CISC or RISC better ? Complexity ? • Which can better exploit hardware features ?

30. Characteristics of Some Example Processors