Test Power

1. Test Power

2. Outline • Test Power Problem: Background and Basics • Increasing Test Power Concerns • Aspects of Test Power Dissipation • DFT techniques targeting test power • Power-aware ATPG • Power Analysis Methodologies and Issues

3. Test Power Problem* • A circuit is designed for certain function. Its design must allow the power consumption necessary to execute that function/application. • Power buses are laid out to carry the maximum current necessary for the function. • Heat dissipation of package conforms to the average power consumption during the intended function. Manufacturing test mode can be/should be viewed as another mode of operation for the circuit with respect to power dissipation. * See [Ravi-VDAT07,Ravi-ITC07] for more information on test power

4. Testing Differs from Function: Functional Mode Other chips VLSI chip System outputs System inputs system Functional outputs Functional inputs

5. Testing Differs from Function: Test Mode Packaged or unpackaged device under test (DUT) DUT output for comparison with expected response stored in ATE VLSI chip Test vectors: Pre-generated and stored in ATE Power Clock Automatic Test Equipment (ATE): Control processor, vector memory, timing generators, power module, response comparator

6. Scan Testing Primary inputs Primary outputs Combinational logic SO D 1 0 DFF mux Q SD Scan-out SO SE Scan flip-flop Scan flip- flops D Q Scan enable SE Scan-in SI Capture Shift-Out Shift-In Sequential Circuit with Scan Scan Flip-Flop An example scan based test During response shift-out, next pattern can be concurrently shifted in. time

7. Functional inputs: Functionally meaningful signals Generated by circuitry Restricted set of inputs May have been optimized to reduce logic activity and power Test vectors: Functionally irrelevant signals Generated by software to test faults Can be random or pseudorandom May be optimized to reduce test time; can have high logic activity May use testability logic for test application Testing Differs from Function: Functional Inputs vs. Test Vectors

8. Terminology* • Design-for-test (DFT): Modifications to the circuit for facilitating test. e.g. scan flip-flop insertion • Automatic Test Pattern Generation (ATPG): Process of automatically generating test patterns that can be applied to the chip • Pattern generation happens on the gate-level netlist of the circuit assuming a certain set of eventual defects/faults • Fault Models: Abstraction of potential defects to ease the task of ATPG • E.g., stuck-at faults, transition faults • Compression: Technology for reduced test data volume/test application time. Compressed patterns are stored on the tester, while on-chip de-compression logic ensures that uncompressed patterns can be applied. * See [Agarwal00] for more information on basics/ advanced concepts in testing

9. Outline • Test Power Problem: Background and Basics • Increasing Test Power Concerns • Aspects of Test Power Dissipation • DFT techniques targeting test power • Power-aware ATPG • Power Analysis Methodologies and Issues

10. Increasing Test Power Concerns 4.1X Example circuit in 65nm technology 3.5X Normalized Power Pattern type • Test power is several times higher than normal mode power • Conflicting requirements of test time reduction practices • Increasing test concurrency • Test multiple modules simultaneously • Increasing frequency of scan shift • Conflicting requirements of test data volume reduction practices • Compression and compaction techniques elevate circuit switching • Tests are run at various stress conditions (voltage and temperature) • Redundant switching in circuit logic during scan shift

11. Increasing Test Power Concerns Amperes Allowable current during test of unpackaged die Allowable current during normal o/p of packaged chip • Peak test power can affect circuit yield • Example: Ti/Siemens 130nm ASIC design with 1M gates + 300kbits SRAM, 150 MHz clock frequency [Saxena-ITC03] • Some transition fault patterns passed only on or near 1.55V • Failure identified to be due to significant IR drop, caused by increased switching in the launch to capture time window. • Example: Power supply voltage drops during scan shift operations [Matsushita-ITC03] • Test power is a determining factor for packaging and power grid design • Power dissipation constraints can also come from a tester standpoint • Power availability during wafer testing smaller [Intel-ITC04] (source: Intel)

12. Outline • Test Power Problem: Background and Basics • Increasing Test Power Concerns • Aspects of Test Power Dissipation • DFT techniques targeting test power • Power-aware ATPG • Power Analysis Methodologies and Issues

13. Aspects of Test Power • Average vs peak power • Average Power Dissipation = (Total Energy Consumed / Total time) • Relevant for reliability issues – temperature effects, EM • Peak Power Dissipation • Max power consumed in a cycle, Instantaneous peak power • Tester implications, packaging implications for field test, IR drop issues can have impact on power grid design • Dynamic power vs Static power • Depends on the PTV corner • At burn-in corner, static power can dominate with low frequency circuit operation! • Leakage power implications • An increasingly major component of static power, that is dependent on the state of the circuit • Glitch power neglected • Arise due to non-zero cell and interconnect delays, imbalance in logic paths • As good as your power analysis flow!

14. Aspects of Test Power • Shift power versus Capture power • Low Frequency Shifts: Average Shift power may be a concern • High Frequency Shifts: Peak and Average power becomes a concern • Capture power: Fast capture pulses in transition patterns cause Peak power (IR drop) issues • Structural Breakdown: Memories, Scan FF vs Combinational logic • Memory power consumption can be dominant • Must be aware of this while scheduling test of multiple memories • Scan FF vs Combinational logic • 78% of the energy dissipated in the combinational logic [Wunderlich99] • 29%-53% of power dissipation seen in combinational logic for industrial designs PERCENTAGE POWER • Power Analysis Times and Logic Simulation Dump Sizes! • Ideally, you need the toggle activity in every test related cycle • Size of VCD dump file (for the TI/Siemens Design) to infer toggle activity in the launch-to-capture time window is 2M !

15. Outline • Test Power Problem: Background and Basics • Increasing Test Power Concerns • Aspects of Test Power Dissipation • DFT techniques targeting test power • Power-aware ATPG • Power Analysis Methodologies and Issues

16. Basic Concept: Prevent switching in the comb. logic during shift Use of blocking circuitry (NOR, MUX) at Q outputs connected to combinational logic Can manifest as part of special scan cells Use of First Level Power Supply Gating [Bhunia05] DFT for test power reduction (1) –Blocking Circuitry EN EN SD SD Q Q D D + Structured Tech (minimal ATPG impact) • Normal Mode Overheads ScanEn EN ScanOut ScanIn EN SQ SD SQ SQ Q D SD Q Scan FF Q D Q SQ Combinational Circuit Enhanced Scan Cells Usage in an Sequential Circuit

17. First Level Power Supply Gating [Bhunia05] (b) GND Gating with Floating output fixup (a) Simplest Version: GND Gating

18. + Does not add delay to the normal path + No significant change to ATPG + Test application time (TAT) impact negligible - Scan segment control implementation needed, routing implications - Delay test considerations (LOC ok) DFT for test power reduction (2) – Scan Segmentation [Whetsel-ITC00] SO1 SI1 CHAIN1, SEGMENT 2 CHAIN1, SEGMENT 1 SO2 SI2 CHAIN2, SEGMENT 1 CHAIN2, SEGMENT 2 SCAN OUTS SCAN INS SOn SIn CHAINn, SEGMENT 1 CHAINn, SEGMENT 2 Gated_clk2 Gated_clk1 SEGMENT2 SEGMENT1 • Basic Concept: Divide a scan chain into multiple segments, and shift them one at at time, while the other segments have their clocks gated. • Clock gating and by pass multiplexors added to provide acccess

19. DFT for test power reduction (3) – Scan chain disable [Sankaralingam02] • If a scan chain is disabled, • It is not clocked, scan chain does not shift/capture • Issue: Deciding on the granularity of scan chain disabling • Inter-core (coarse-grained) versus Intra-core (fine-grained) • Basic Concept: Operate one scan chain at a time (differs from scan segmentation (how?)

20. CELL Processor SPE Each SPE has 150k latches 24 scan chains in LBIST mode Thold signal: When active, it will stop the clock to the latch element Example: Scan Chain Disable in CELL processor [IBM-ITC06]

21. Something to think about …. • Can you think of DFT options that can help reduce test power? • What trade-offs will you usually worry about?

22. Outline • Test Power Problem: Background and Basics • Increasing Test Power Concerns • Aspects of Test Power Dissipation • DFT techniques targeting test power • Power-aware ATPG • Power Analysis Methodologies and Issues

23. Power-aware ATPG: Significance of Care Bits • Test patterns consist of care bits and don’t care bits • E.g., a pattern (0XXX1XX) has 5 don’t care bits and 2 care bits • The way the care bits are populated will affect ATPG quality and also have an impact on power • For e. g., Random Fill (randomly filling care bits) may help in fortuitous detection of faults, but at higher power consumption costs. [source: Butler-ITC04] Fraction of care bits present Fraction of care bits present ATPG pattern # (as APTG progresses) Percentage of Patterns

24. Power-aware ATPG: Fill Techniques • Different kinds of fill techniques can be used • Random fill: Fill in randomly • Zero fill: Fill in don’t care bits with ‘0’ • One fill: Fill in don’t care bits with ‘1’ • Adjacent fill: Fill in don’t care bits with the value of the nearest care bit. (Example: 0XXX1XX will be 0000111) Module D: 600k gates, 8 scan chains, scan chain length 2970 Module M: 600k gates, 8 scan chains, scan chain length 3271 Fraction of cells switching in 11 from all patterns during launch-to-capture cycle Fraction of cells switching in 3 of the first 1000 patterns during launch-to-capture cycle • Fill adjacent performs better than other heuristics along various dimensions [Butler-ITC04].

25. Power-aware ATPG: Fill Techniques • Earlier Example: IR drop issue with TI/Siemens ASIC • Transition pattern caused increased switching during launch-to-capture time window Source: [Saxena-ITC03] Increasing No. of 0s placed in “non-essential” Scan cells

26. Inadequacy of Existing Low-Power ATPG Techniques [Ravi-ICCAD07] Variation of Power with fill techniques for compacted patterns for an example module from a TI design 0.9% Design A Power (mW) Design B Power (mW) 12% Dynamic Power (milliWatts) Last 5 patterns First 5 patterns Variation of Power with Fill Techniques for Two Designs Supporting Compression • Ineffectiveness of fill techniques for compressed and compacted patterns • Compaction increases bit utilization in a pattern for testing more faults • Compression reduces control over don’t care bits due to requirement for driving multiple scan chains

27. Low Power ATPG Using Activity Threshold Controls [Ravi-ICCAD07] • Goals: • To come up with low power ATPG techniques which are better than fill techniques • No modification to ATPG tool should be required • Benefit the generation of low power patterns even in compressed and compacted scenarios Toggle Distribution using Fill Techniques for an Example Circuit Reduced Activity Toggle Distribution for an Example Circuit Using the Proposed Framework

28. General Observations POWER CONSTRAINT CIRCUIT ENHANCED NETLIST FOR ATPG POWER THRESHOLD INPUTS Monitored Signals Power Constraint Circuit Target Circuit Meet Constraint (Y/N)? [Constrained as Y for ATPG tool] OUTPUTS SF1 adder tree • Power constraints are simple mathematical computations. Example:Thresholded transition count for a scan out operation • Power constraints can be encapsulated as a circuit themselves (aka Power Constraint Circuits or PCC) • Force ATPG tool to generate patterns on a circuit that includes target circuit+PCC SF2 transition count SF3 tc_out SFN τ

29. Low Power ATPG Methodology • Exploits the capabilities of the power constraint circuit (PCC) to perform both pattern filtering and pattern generation

30. Outline • Test Power Problem: Background and Basics • Increasing Test Power Concerns • Aspects of Test Power Dissipation • DFT techniques targeting test power • Power-aware ATPG • Power Analysis Methodologies and Issues

31. Background: Status of Test Power Analysis Flows Yes Architecture Level No (at present) RTL Yes Gate-Level Usability for Test Power Estimation Power Estimation options Estimation Time Accuracy Gap • Several power estimation choices available for functional use cases • Gaps in test power analysis flows • RTL option not available yet • Architecture-level test power calculators way off • Current Status: • Gate-level power estimators remain the best bet.

32. Gate-level Test Power Estimation Flow (Conventional) Gate-Level Netlist Test Pattern Generation Step 1 TDL Simulation Step 2 Dump Format Conversion Step 3 Gate-Level Power Estimator Step 4 Power Report • Conventional flow adopted to perform gate-level test power estimation is simulation-based • Four main steps as shown in the figure • Step 3 (dump format conversion) is optional • For average test power consumption, shift power due to a scanout operation is calculated • The time interval of interest can be specified as an input in Steps 1/2/3 • Estimation is performed at various PVT corners • Challenges for multi-million gate SoCs: • Time-consuming • Dump sizes can be very large

33. Summary • Test power consumption is a very important aspect of chip design cycle • Four facets of test power consumption • Test preparation/planning: Understanding the requirements • Power-aware DFT • Low-Power ATPG • Test Power Analysis • What we did not cover today? • Test implications of power management circuitry

34. References • Books on Testing • [Agarwal00] Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits by Bushnell and Agrawal, Springer, 2000 • Survey Papers/Articles • [Ravi-VDAT07] S. Ravi, “Addressing Test Power Issues in Digitial CMOS Design”, to appear in Proc. VLSI Design and Test Symposium (VDAT), 2007. • [Ravi-ITC07] S. Ravi, “Power-aware Testing: Challenges and Solutions”, (invited lecture series), to appear in Proc. International Test Conference (ITC), 2007. • [Jackson-07] T. Jackson, “Design-with-test for low-power devices”, EE Times-Asia, Jan 2007. • [Butler-ITC04] K. M. Butler, J. Saxena, T. Fryars, G. Hetherington, A. Jain, and J. Lewis, “Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques”, Proc. International Test Conference, pp. 355-364, 2004. • DFT • [Wunderlich99] S. Gerstendorfer and H. –J Wunderlich, "Minimized power consumption for scan-based BIST," Proc. International Test Conference, pp.77-84, 1999. • [Whetsel-ITC00] L. Whetsel, Adapting scan architectures for low power operation, Proc. International Test Conference, pp. 863-872, 2000. • [IBM-ITC06] C. Zoellin, H. -J Wunderlich, N. Maeding and J. Leenstraa, “BIST Power Reduction Using Scan-Chain Disable in the Cell Processor,” Proc. International Test Conference, 2006. • [Bhunia05] S. Bhunia, H. Mahmoodi, D. Ghosh, S. Mukhopadhyay, and K. Roy, “Low Power Scan Design Using First Level Supply Gating”, IEEE Trans. onVLSI Systems, March 2005. • [Sankaralingam02] R. Sankaralingam and N. Touba, “Reducing Test Power During Test Using Programmable Scan Chain Disable”, Proc. DELTA, pp. 159-166, 2002. • [Yoshida-ITC03]T. Yoshida and M. Watati, "A new approach for low-power scan testing," Proc. International Test Conference, pp. 480- 487, 2003.

35. References • Low-Power ATPG • [Saxena-ITC03] J. Saxena et al, “A Case Study of IR-Drop in Structured At-Speed Testing”, Proc. International Test Conference, pp. 1098-1104, 2003. • [Ravi-ICCAD07] S. Ravi, V. Devanathan, and R. Parekhji, “Methodology for Low Power Test Pattern Generation Using Activity Threshold Control Logic”, to appear in Proc. International Conference on Computer-Aided Design (ICCAD), 2007. • Misc • [Intel-ITC04] S. Kundu, T. M. Mak, and R. Galivanche, "Trends in manufacturing test methods and their implications," Proc. International Test Conference, pp. 679- 687, Oct. 2004.