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Agenda

Agenda. Last Year’s Mission. The Road Ahead. Summary. 1.2. 1. 0.8. 0.6. 0.4. 0.2. 0. 1990. 1992. 1994. 1996. 1998. 2000. 2002. Last Year’s Mission Accomplished. Process Leadership Density Leadership Performance Leadership Price & Value Leadership Software Leadership.

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Agenda

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  1. Agenda Last Year’s Mission The Road Ahead Summary

  2. 1.2 1 0.8 0.6 0.4 0.2 0 1990 1992 1994 1996 1998 2000 2002 Last Year’s Mission Accomplished • Process Leadership • Density Leadership • Performance Leadership • Price & Value Leadership • Software Leadership Feature Size (micron) 5v 3.3v 2.5v 1.8v 1.3v

  3. 75 50 25 7.5 3Q98 4Q97 1Q98 2Q98 4Q98 Process Leadership Virtex 1 Million Gate 0.25u Process XC40250XV XC40150XV Transistor Count (millions) “samples today” XC40125XV

  4. 10M 2M 1M 500k 250k 180k Density Leadership 10M Gates In 2002 Virtex II Density (system gates) Virtex XC40250XV XC40125XV XC4085XL 1997 1998 1999 2000 2002 10 Million System Gates in 2002!

  5. Architecture Innovation Leadership • Reconfigurable Logic • On-Chip A/D-D/A • Embedded Functions • 1GHz Diff. Interface • Built-in Logic Analyzer • 133 MHz Block Dual Port RAM • System I/O (LVTTL, SSTL, GTL) • Vector Based Interconnect • Phase Locked Loops • 66 MHz 64-Bit PCI Features • Distributed Dual Port RAM • I/O Registers • Internal Bussing • 5V Tolerant I/O • 3.3V and 5V PCI 1998 1999 2000 2001 2002

  6. 300 200 280 180 260 160 240 140 220 120 100 80 60 40 20 0 2001 2002 1995 1996 1997 1998 1999 2000 Performance LeadershipEnabling high performance solutions first • PC 100 SDRAM Compliant • 100 MHz DSP for Wireless Base Station • 33 MHz PCI • 2002 System Standards • 233 MHz uP • 300 MHz RAM I/F System Clock Rate* (MHz) • 133 MHz SDRAM I/F • 155 MHz SONET • 66 MHz PCI * 1/(Tsetup+Tclock-to-out)

  7. Quality & Reliability LeadershipWorldclass Today & Tomorrow Description Industry Standard Xilinx Today Xilinx Future AOQL* < 25 ppm < 3.4 ppm < 3.4 ppm Reliability < 100 FITs < 10 FITs < 10 FITs Moisture JEDEC Level 3 JEDEC Level 3 JEDEC Level 2 Resistance ISO Certification Some 9001 & 9002 9001 & 9002 QML Certification No Yes Yes Delivery by OFD** No 95% > 95% * Average Outgoing Quality Level ** Original Factory Commit Date

  8. HQFP PQFP PLCC PGA BGA Packaging Leadership Pins Flip Chip Technology 1000 Chip Scale Fine Pitch BGA 700 <0.8mm SBGA 1.0mm 500 1.27mm 300 100 1998 2000 2002

  9. 1997 1998 1999 2000 2001 2002 Priced for High-Volume Leadership 200K • New Applications • Set Top Box • DVD • Digital Camera • PC Peripherals • Consumer Electronics 100K Density (System Gates) 60K 100K 60K 25K 40K 10K Gates/$ in 2002! 15K 100K unit volume price projections

  10. Without Compromises Pricing competitive with ASICs High Performance On-chip SelectRAMTM PCI LogiCORE + AllianceCORE FPGA Price Leadership Spartan $395 SpartanXL $295 0.5 3LM More Features 5 Volt Price Spartan-II < $200 Spartan Next Generation < $150 0.35 5LM 3.3 Volt 0.25 5LM 0.18 2.5 Volt 1.8 Volt 1998 1999 2000 2001 2002 *Prices are for 5K system gates, 100K units, -3 speed, Lowest Cost Package

  11. Without Compromises Flexible ISP tPD = 4ns Best Pin-Locking Industry Standard JTAG 1998 1999 2000 2001 2002 CPLD Price Leadership $15 XC95216/XL Price $7 $1.80 XC9536/XL $0.80 * Prices are based on 100Ku+, slowest speed grade, lowest cost package

  12. Software Leadership • Team Based Design • Modular Guide • Modular Compile • HDL- Centric Flows • Largest Installed Base • Highest Circuit Performance with M1 • Fastest Timing Driven Compile Times • Shrink-Wrapped FPGA Express • Best flows & QOR with leading EDA vendors • Push Button Design 1998 2000 2002

  13. Release 1.5 is Hot • 5 New FPGA/CPLD Families • 2x Runtime Improvements • Graphical Constraints Editor • Floorplanner • Automatic Pin Locking • 6x Faster Timing Analysis (Kpaths algorithm) • Automatic Clock Skew Handling • New Reporting of Minimum Delays • Voltage and Temperature Speed Pro-rating

  14. Compile Time Leadership 100 90 80 Up to 6X faster than 1.3 70 60 Minutes* 50 40 30 20 10 0 Release 1.4 1.5 2.1 2.2 * 100k System gate designs (200MHz Pentium) And with ... 1999 Goal: 1 Million Gates in 45 minutes! Faster CPUs Faster Compile Times Modular Compile

  15. The Road AheadDesign Methodology Evolution .25u 500K 100K 25K Density (system gates) .35u .5u Process Technology

  16. Complete Core SolutionsReduce Time To Market Design From Scratch Learn Design Implement Verify Reference Design, Generic Core L D I V Complete FPGA Core Solution L D I V Months Pre-verified Designs Area & Timing Optimized Complete & Flexible Design Little Knowledge of Function Required

  17. Xilinx Smart-IP Delivers Intelligent Software Implementation Architectures tailored to cores Flexible Core Technology Xilinx Smart-IP Technology High Predictability High Flexibility High Performance Available Only From Xilinx

  18. Architecture Tailored to Cores Segmented Routing • Advantages • Efficient Routing • Predictable Timing • Low Power Core1 Core2 Non-Segmented Routing Xilinx Segmented Routing Distributed Memory • Advantages • Portable RAM based Cores • Improved Logic Efficiency by 16X • High Performance Cores RAM available locally to the Core

  19. Fixed Placement & Pre-defined Routing Fixed Placement Relative Placement I/Os Guarantees Performance Guarantees I/O & Logic Predictability Other Logic Has No Effect on the Core Intelligent SoftwarePre-defined Placement & Routing Enhances Performance & Predictability

  20. Flexible Core TechnologyOptimal Core Creation & Flexible Core Delivery Data sheets Parameterized Cores CoreLINX: Web Mechanism to Download New Cores SystemLINX: Third Party System Tools Directly Linked With Core Generator Free Software & Free Cores Included (Cores offer over a 1,000,000 Permutations!)

  21. Performance Independent of a Core’s Placement or the number of cores used in the Device Smart-IP Delivers Design Portability 80 MHZ 80 MHZ 80 MHZ 80 MHZ Performance Independent of Device Size Non-Segmented Architecture May Experience 30% Performance Degradation

  22. Leader in Core SolutionsXilinx and Partners’ COREs • 82xx, UARTs, DMA, • 66 MHz DRAM/SDRAM I/F • Memory (RAM, ROM, FIFO) • Micro Sequencer (2901) • Proprietary RISC Processors • Microprocessor I/Fs • 8051/8031 • IEEE 1284 • MIPS • 133+ MHz SDRAM I/F Base Level Functions • Advanced Processors • ATM Cell Assembly/Delineation • CRC-16/32 • T1 Framer • HDLC • Reed-Solomon, Viterbi • UTOPIA, 25/33/50 MHz • 10/100 Ethernet • 1Gb Ethernet • ADSL, HDSL, XDSL • ATM/IP Over SONET • SONET OC3/12 • Modems • SONET OC48 • Emerging Telecom • and Networking • Standards Communication & Networking • Add, Subtract, Integrate • Correlators • Filters: FIR, Comb • Multipliers • Transforms: FFT, DFT • Sin/Cos • DCT • Cordic • DES • Divider • JPEG • NCO • DSP Processor I/Fs • DSP Functions > 200 MSPS • Programmable DSP Engines • QAM DSP Functions • Satellite decoders • Speech Recognition • CardBus • FireWire(100-400 Mbps) • PCI 64bit/66MHz • PC104 • VME Standard Bus Interfaces • CAN Bus • ISA PnP • I2C • PCI 32bit • Emerging High- • Speed Standard • Interfaces • PCMCIA • USB 2000 1999 1998 By 2002: Virtually All Functions Available as Cores

  23. Xilinx Applications on The Rise From Standard Products & Gate Arrays to Systems on a Programmable Chip

  24. Simple & Fast Low Cost CPLD Solutions • Variances In Interfaces • SDRAM (i.e. Bank vs. SIMM) • Unique System Back-End Isolates User From Interface Issues • Critical Signal Timing • Electrical Interfacing • Control Signal Sequencing (State Machine Design)

  25. Flexible High Density FPGA SolutionsJPEG Compression (70k ASIC Gates + RAM) FPGA Advantages over Chipsets • Can specify Non-Standard Data-Rate & Pixel Depth • Industrial Temp Range • High Performance • 2x NTSC Video Resolution • 1.5x NTSC Pixel Depth

  26. High Value Applications with Spartan XCS30XL Price Percentage of Device Used Effective Function Cost Core Function UART $6.95 17% $1.20 $6.95 $2.50 16-bit RISC Processor 36% $6.95 27% $1.90 16-bit, 16-tap Symmetrical FIR Filter Reed-Solomon Encoder $0.40 6% $6.95 PCI Interface (w/ faster speed grade) $12.00 45% $5.40

  27. $20 $15 $10 $5 Costs less Than Standard ICs! External PLD15K Gates Standard ChipPCI Master I/F Component Cost 100K Units User Design15K Gates PCI Master I/F Standard Chip Solution>$20 Xilinx PCI Solution<$13.50

  28. Delivers High PerformanceAt a Fraction Of The Cost 1.6 • Integrated System Level Tools • Easy Parameterization Tools • Free Parameterization 1.2 Giga-MACs $192* $9.95* 0.8 0.4 1 Extra uP 2 Extra uPs 3 Extra uPs * Prices based on 50k volume

  29. The Road AheadDesign Methodology Evolution .18u 1 Million .25u 500K Process Technology Density (system gates)

  30. Xilinx Enables Modular Design • Facilitates Group Design & Reuse • Seamless Integration Between Modules • Extension to leading cores solution • Modular Time Specs • With industry’s best timing constraint language • Modular Incremental Compile • Extensive R&D investment Designer1 Module Designer2 Module Design Reuse Designer3 Module Reduces Compile Time & Increases Performance

  31. VirtexThe Ideal Platform for Modular Design • Fast I/O Performance • Phase Lock Loops • 155MHz SONET • 133MHz SDRAM • 66MHz PCI • Predictably Fast Performance • Vector Based Interconnect • 10ns Global Signals • 100MHz+ from all devices • Flexible Interfaces • LVTTL, LVCMOS • SSTL, GTL, PCI • Future Standards • Flexible, Fast RAM • 133MHz External, Block, and Distributed RAM • Fully Dual Ported (2 independent read/write ports) • Configurable Data Widths and Depths • SSTL3 Interface to External RAM

  32. VHDL Design Environment Verilog Design Environment CoreGen New Modules Designer #1 Designer #2 DSP FIFO IP Modules Design Reuse AllianceCore 133Mhz SDRAM CPU Gbit Ethernet LogiCore 66Mhz PCI Virtex Enables System on a Programmable Chip 160 MHz I/O Performance 133 MHz Memory Performance 1 Million System Gates

  33. HardWire FpgASIC’sThe only ASIC solution designed for Virtex FPGA HardWire FpgASIC Logic Gbit Ethernet SDRAM 133Mhz SDRAM Logic • Functional FPGA Equivalence • Support for Complex FPGA Cores • Risk and Resource Reduction • No Re-engineering from FPGA • CLB Integrity Maintained • Planned for 2H 2000 Introduction

  34. Virtex FPGA 50K units HardWire FpgASIC 100K units $300 $250 $200 $150 $100 $50 $0 Virtex + FpgASICCost Effective System on a Chip 1 Million Gates 800K Gates 600K Gates 400K Gates 2001 2002 2001 2002 2001 2002 2001 2002

  35. The Road AheadDesign Methodology Evolution 10 Million 1 Million .15u .18u

  36. Increased Integration Time Requires Team Based Design Integration Time Design Time Total Development Time 10k 100k 1M 10M 100M System Gates

  37. Xilinx To DeliverTeam Based Design Solutions Team Oriented Design Mgmt • Engineering Change Control Timing Budget Calculator • Module Based Timing Redistribution Module Timing Independence • Fixed Timing On a Module Auto Inter-Team Floorplanning Global Timing Defn & Optimization

  38. Xilinx Delivers • Committed to Product Leadership • Focused on Complete Solutions • Driving New Applications With Cores • Delivering the Vision Real Technology Partnerships

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