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L. Ratti

Interconnection of a 3D front-end chip to edgeless/slim-edge and CMOS sensors with advanced techniques. L. Ratti. Università degli Studi di Pavia and INFN Pavia. 2 nd Annual Meeting 10-12 April 2013, INFN-LNF, Frascati , Italy. for the IPHC-IRFU / INFN collaboration. OUTLINE.

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L. Ratti

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  1. Interconnection of a 3D front-end chip to edgeless/slim-edge and CMOS sensors with advanced techniques L. Ratti Università degli Studi di Pavia and INFN Pavia 2nd Annual Meeting • 10-12 April 2013, INFN-LNF, Frascati, Italy for the IPHC-IRFU/ INFN collaboration OUTLINE Overview of the project Status of sensor and readout chip design Test of 3D prototypes Progress with the T-Micro vertical integration process

  2. Goal of the project Design and fabrication of a multi-tier pixel sensor resulting from the vertical interconnection of a readout chip and of a sensing layer CMOS readout chip, based on a 130 nm vertically integrated process (Tezzaron/Globalfoundries) vertical interconnection process (m-bumps by T-Micro) CMOS sensing layer (XFAB, 350 nm, or an alternative process in 180 nm) edgeless (or 3D slim edge) fully depleted, planar silicon detector (from FBK, Trento) The project is to be regarded mainly as R&D, although the proposed device is aimed for applications to experiments at the next generation colliders – SuperB, HL-LHC

  3. Tezzaron vertical integration (3D) technology TSV WB/BB pad In wafer-level, three-dimensional processes, multiple strata of planar devices are stacked and interconnected using through silicon vias(TSV) 3D processes rely upon the following enabling technologies Inter-tier bond pads Fabrication of electrically isolated connections through the silicon substrate (TSV formation) Substrate thinning (below 50μm) Inter-layer alignment and mechanical/electrical bonding 1st wafer Tezzaron Semiconductor technology (via middle approach, vias are made between CMOS and BEOL) can be used to vertically integrate two 130 nm CMOS layers specifically processed by Globalfoundries 2nd wafer Globalfoundries provides a 130 nm CMOS process with several different options; chosen one features 1 poly, 6 metal layers, 2 top metals, dual gate (core and thick oxide devices, 3.3 V), N- and PMOS with different Vth

  4. Superpix1 readout chip • 32x128 elements (2 sub-matrices 16x128), 3.5 x 10 mm2 chip area Hybridpixels single MOS 3.25x2 mm2 DNW MAPS 3.25x2 mm2 The readout block is designed to sustain 100 MHz/cm2 hit rate and 100 ns resolution Superpix1, front-end for hybridpixels 128x32 pixels 10x3.5 mm2 • Data are sent to 4 sparsifiers, each managing 32 rows (corresponding to 8 zones, Wzone=4 pixels) • VHDL simulation of the digital readout block, together with a functional description of the cell matrix, is in progress – P&R to be performed soon ApselVI, DNW MAPS matrix with fast sparsified readout 128x96 pixels 10x5.2 mm2

  5. Superpix1 analog front-end

  6. Superpix1 analog front-end: cell layout

  7. High resistivity edge sensors Planar, p-on-n pixel detectors to be vertically integrated with Superpix1 have been fabricated and are under test – vertical integration with T-Micro (also compatible with IZM process) 128x128 Process test structures 32x128 Characterization of prototype active edge sensors is in progress; new sensors to be designed after some feedback from the tests; fabrication to start after FBK clean room re-opening (6-inch process) Process test structures 222x128 7

  8. Test structures from the 3DIC consortium run 1st wafer metal + oxide +2nd wafer

  9. 3D DNW MAPS: readout functionality tests Full functionality of vertically integrated chip demonstrated

  10. 3D DNW MAPS: analog front-end characterization • Charge sensitivity: 250 mV/fC • Input dynamic range: 1500 electrons • ENC: 40 electrons rms

  11. 3D CMOS process: radiation hardness tests Single NMOS and PMOS transistors fabricated with the Tezzaron/Globalfoundries process Irradiated with gamma-rays form a 60Co source (up to 50 Mrad) Also DNW MAPS have been irradiated and tested

  12. Vertical integration with T-Micro Very high interconnect density, with small bond pads (squares with a side of 5 or 10 μm, depending on the bump size, 2x2 μm2 or 8x8 μm2) both on the sensor and the readout sides  more room for top metal routing, in particular for power and ground lines, smaller capacitive coupling, less material

  13. Alignment rules Markers for rough and fine alignment (through IR imaging)- apparently not mandatory

  14. Vertically integrated layers Preliminary test of the T-Micro integration process performed on pre-existing readout chips (Superpix0) and high resistivity n-on-n pixel sensors (VPix1) Sensors in the red box have no metal layers under the markers Superpix0 chip layout Front-end chips and a pixel sensor wafer shipped to T-Micro in Dec. 2012 6verticallyintegrated chips havebeenshipped back to Italy, tests are in progress

  15. Surface inspection and alignment

  16. Conclusion Design of the front-end chip is progressing quickly, chip design completion is expected for end of June – submission date not set yet, but October might be the right time Recent results from the characterization of 3D DNW MAPS demonstrated that vertical integration performed by Tezzaron and Ziptronix works – new samples vertically integrated by Tezzaron to be tested soon Tests on chips vertically integrated by T-Micro (Superpix0 front-end + Vpix pixel sensor) are in progress

  17. Backup slides

  18. Financial structure of the project

  19. Timescale For each task in the table, the delivery time with respect to the AIDA project start date is indicated

  20. The 3D-IC collaboration Several groups from US and Europe have been involved in the first 3D MPW for HEP (pixel and strip readout chips for ATLAS, CMS, B-factory, ILC) and photon science applications (X-ray imaging) ~ 3.2 cm Single set of masks used for both tiers to save money identical wafers produced by Chartered (now Globalfoundries) and face-to-face bonded by Tezzaron backside metallization by Tezzaron ~ 2.5 cm

  21. DNW MAPS test structures Small test structures single pixels with and w/o detector emulating capacitor shunting the readout channel input (analog only) 3x3 DNW MAPS matrices (analog only, for charge collection tests) 8x8 and 16x16 DNW MAPS matrices (analog and digital, for readout architecture test) ~ 5.2 mm ~ 6.3 mm 1st wafer metal + oxide +2nd wafer substrate

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