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Lecture #8 Agenda VHDL : Operators VHDL : Signal Assignments Announcements Next is Quiz1

ECE 4110–5110 Digital System Design. Lecture #8 Agenda VHDL : Operators VHDL : Signal Assignments Announcements Next is Quiz1. VHDL Operators.

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Lecture #8 Agenda VHDL : Operators VHDL : Signal Assignments Announcements Next is Quiz1

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  1. ECE 4110–5110 Digital System Design Lecture #8 • Agenda • VHDL : Operators • VHDL : Signal Assignments • Announcements • Next is Quiz1

  2. VHDL Operators • VHDL Operators- Data types define both "values" and "operators" - There are "Pre-Determined" data types Pre-determined = Built-In = STANDARD Package- We can add additional types/operators by including other Packages- We'll first start with the STANDARD Package that comes with VHDL

  3. VHDL Operators • Logical Operators- works on types BIT, BIT_VECTOR, BOOLEAN- vectors must be same length- the result is always the same type as the input not and nand or nor xor xnor

  4. VHDL Operators • Numerical Operators - works on types INTEGER, REAL- the types of the input operands must be the same + "addition" - "subtraction" * "multiplication" / "division" mod "modulus" rem "remainder" abs "absolute value" ** "exponential" ex) Can we make an adder circuit yet? A,B : in BIT_VECTOR (7 downto 0) Z : out BIT_VECTOR (7 downto 0) Z <= A + B;

  5. VHDL Operators • Relational Operators - used to compare objects- objects must be of same type- Output is always BOOLEAN (TRUE, FALSE)- works on types: BOOLEAN, BIT, BIT_VECTOR, CHARACTER, INTEGER, REAL, TIME, STRING = "equal" /= "not equal" < "less than" <= "less than or equal" > "greater than" >= "greater than or equal"

  6. VHDL Operators • Shift Operators - works on one-dimensional arrays- works on arrays that contain types BIT, BOOLEAN- the operator requires 1) An Operand (what is to be shifted) 2) Number of Shifts (specified as an INTEGER)- a negative Number of Shifts (i.e., "-") is valid and reverses the direction of the shift sll "shift left logical" srl "shift right logical" sla "shift left arithmetic" sra "shift right arithmetic" rol "rotate left" ror "rotate right"

  7. VHDL Operators • Concatenation Operator - combines objects of same type into an array- the order is preserved & "concatenate" ex) New_Bus <= ( Bus1(7:4) & Bus2(3:0) )

  8. VHDL Operators • STD_LOGIC_1164 Operators - To expand the data types we have in VHDL, we include the IEEE Package "STD_LOGIC_1164"- This gives us the data types: STD_LOGIC STD_LOGIC_VECTOR- This gives us all of the necessary operators for these types Logical Numerical Relational Shift

  9. VHDL Operators • Examples • Example 1 v := a + y * x; • The multiplication y*x is carried out first, then a is added to the result of multiplication. • This is because the multiplication operator has higher level of priority than the adding operator. • Example 2 variable We1, We2, We3, Wy : BIT := '1';Wy := We1 and We2 xnor We1 nor We3; • For the initial value of the variables We1, We2, We3 equal to '1', the result is assigned to the variable Wy • and is equal to '0'. • Example 3 variable Zm1: REAL := 100.0;variable Zm2 : BIT_VECTOR(7 downto 0) := ('0','0','0','0','0','0','0','0');variable Zm3, Zm4 : BIT_VECTOR(1 to 0);Zm1 /= 342.54 -- TrueZm1 = 100.0 -- TrueZm2 /= ('1', '0', '0', '0', '0', '0', '0', '0') -- TrueZm3 = Zm4 -- True

  10. VHDL Operators • Example 4 Zm1 > 42.54 -- TrueZm1 >= 100.0 -- TrueZm2 < ('1', '0', '0', '0', '0', '0', '0', '0') -- TrueZm3 <= Zm2 -- True • Example 5 variable Zm5 : BIT_VECTOR(3 downto 0) := ('1','0','1','1');Zm5 sll 1 -- ('0', '1', '1', '0')Zm5 sll 3 -- ('1', '0', '0', '0')Zm5 sll -3 -- Zm5 srl 3Zm5 srl 1 -- ('0', '1', '0', '1')Zm5 srl 3 -- ('0', '0', '0', '1')Zm5 srl -3 -- Zm5 sll 3Zm5 sla 1 -- ('0', '1', '1', '1')Zm5 sla 3 -- ('1', '1', '1', '1')Zm5 sla -3 -- Zm5 sra 3Zm5 sra 1 -- ('1', '1', '0', '1')Zm5 sra 3 -- ('1', '1', '1', '1')Zm5 sra -3 -- Zm5 sla 3Zm5 rol 1 -- ('0', '1', '1', '1')Zm5 rol 3 -- ('1', '1', '0', '1')Zm5 rol -3 -- Zm5 ror 3Zm5 ror 1 -- ('1', '1', '0', '1')Zm5 ror 3 -- ('0', '1', '1', '1')Zm5 ror -3 -- Zm5 rol 3

  11. VHDL Operators • Example 6 constant B1: BIT_VECTOR := "0000"; -- four element arrayconstant B2: BIT_VECTOR := "1111"; -- four element arrayconstant B3: BIT_VECTOR := B1 & B2; -- eight element array, ascending-- direction, value "00001111"subtype BIT_VECTOR_TAB is BIT_VECTOR (1 downto 0);constant B4: BIT_VECTOR_TAB := "01";constant B5: BIT_VECTOR:= B4 & B2; -- six element array, descending-- direction, value "011111"constant B6 : BIT := '0' ;constant B7 : BIT_VECTOR := B2 & B6;-- five element array, ascending-- direction, value "11110"constant B8: BIT := '1';constant B9: BIT_VECTOR := B6 & B8; -- two element array, ascending-- direction value "01“

  12. VHDL Operators • Example 7 z := x * ( -y) -- A legal expressionz := x / (not y) -- A legal expression • The same expressions without parentheses would be illegal. • Example 7 variable A,B :Integer;variable C : Real;C:= 12.34 * ( 234.4 / 43.89 );A:= B mod 2; • Example 8 2 ** 8 = 2563.8 ** 3 = 54.8724 ** (-2) = 1 / (4**2) = 0.0625

  13. VHDL Operators • Assignment Operators- The assignment operator is <=- The Results is always on the Left, Operands on the Right- Types need to all be of the same type- need to watch the length of arrays! Ex) x <=y; a <= b or c; sum <= x + y; NewBus <= m & k;

  14. Delayed Assignments • Delay Modeling- VHDL allows us to include timing information into assignment statements- this gives us the ability to model real world gate delay- we use the keyword "after" in our assignment followed by a time operand. Ex) B <= not A after 2ns;- VHDL has two types of timing models that allow more accurate representation of real gates 1) Inertial Delay (default) 2) Transport Delay

  15. Delayed Assignments • Inertial Delay- if the input has two edge transitions in less time than the inertial delay, the pulse is ignored said another way…- if the input pulse width is smaller than the delay, it is ignored- this models the behavior of trying to charge up the gate capacitance of a MOSFET ex) B <= A after 5ns; any input pulse in signal A with less than 5ns duration will be ignored.

  16. Delayed Assignments • Transport Delay- transport delay will always pass the pulse, no matter how small it is.- this models the behavior of transmission lines- we have to explicitly call out this type of delay using the "transport" keyword ex) B <= transport A after 5ns; B <= transport not A after t_delay; -- here we used a constant

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