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The WSU LC R&D program

Learn about the WSU LC R&D program focusing on Silicon technology applications for solid state tracking. Explore their work on STAR-SVT and Silicon Drift Detectors.

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The WSU LC R&D program

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  1. R.Bellwied, June 30, 2002 The WSU LC R&D program • Who are we ? • What have we done ? • What would we like to do ? • Hardware and Software Rene Bellwied, Dave Cinabro, Vladimir Rykov Wayne State University

  2. R.Bellwied, June 30, 2002 The WSU LC R&D program • Mix of NSF funded HE group and DoE funded Nuclear group • Interest: application of Silicon technologies to large area solid state tracking. • Group was funded by Prescott Committee and NSF in the past two years to conduct LC R&D. Vladimir was partially funded by this grant. • Nuclear group designed, constructed, installed and operates the STAR-SVT ($7 Million project, 50 people from 9 institutions, project started in 1993 and was completed in 2001, Rene Bellwied was project leader throughout this time. Collaborating institutions: BNL, LBNL, Ohio State, University of Texas in Austin, Sao Paulo, Dubna, Protvino, Warsaw University)

  3. R.Bellwied, June 30, 2002 The SVT in STAR Construction in progress Connecting components

  4. R.Bellwied, June 30, 2002 The SVT in STAR (Feb.2001) The final device…. … and all its connections

  5. R.Bellwied, June 30, 2002 STAR-SVT characteristics • 216 wafers (bi-directional drift) = 432 hybrids • 3 barrels, r = 5, 10, 15 cm, 103,680 channels, 13,271,040 pixels • 6 by 6 cm active area = max. 3 cm drift, 3 mm (inactive) guard area • max. HV = 1500 V, max. drift time = 5 ms, (TPC drift time = 50 ms) • anode pitch = 250 mm, cathode pitch = 150 mm • SVT cost: $7M for 0.7m2 of silicon (3 year R&D, 5 year construction) • Radiation length: 1.4% per layer • 0.3% silicon, 0.5% FEE (Front End Electronics), • 0.6% cooling and support. Beryllium support structure. • FEE placed beside wafers. Water cooling.

  6. R.Bellwied, June 30, 2002 SDD’s: 3-d measuring devices(a solid state TPC)

  7. R.Bellwied, June 30, 2002 A typical pattern on a hybrid for a central Au-Au event • central event: inner layer: ~15 hits/hybrid (middle: 8 hits, outer: 5 hits) • = overall track multiplicity = 1000/event

  8. R.Bellwied, June 30, 2002 Typical SDD Resolution

  9. R.Bellwied, June 30, 2002 Wafers: B and T dependence • Operated at B=6T in E896 at the AGS. B fields parallel to drift increase the resistance and slow the drift velocity. • The detectors work well up to 50oC but are also very T-dependent. T-variations of 0.10C cause a 10% drift velocity variation • Detectors are operated at room temperature in STAR. • We monitor these effect via MOS charge injectors

  10. R.Bellwied, June 30, 2002 Present status of technology STAR (completed in 2001) • 4in. NTD material, 3 kWcm, 280 mm thick, 6.3 by 6.3 cm area • 250 mm readout pitch, 61,440 pixels per detector • SINTEF produced 250 good wafers (70% yield) ALICE (to be completed in 2006) • 6in. NTD material, 2 kWcm, 280 mm thick, 280 mm pitch • CANBERRA produced around 100 prototypes, good yield Future (NLC) • 6in. NTD, 150 micron thick, any pitch between 200-400 mm • 10 by 10 cm wafer

  11. R.Bellwied, June 30, 2002 Silicon detector option for LCD Central tracker: Silicon Drift DetectorsFive layers Radiation length / layer = 0.5 % sigma_rphi = 7 mm, sigma_rz = 10 mm             Layer Radii    Half-lengths             -----------    ------------              20.00 cm      26.67 cm              46.25 cm        61.67 cm              72.50 cm        96.67 cm              98.75 cm       131.67 cm             125.00 cm       166.67 cm 56 m2 Silicon Wafer size: 10 by 10 cm # of Wafers: 6000 (incl. spares) # of Channels: 4,404,480 channels (260 mm pitch)

  12. R.Bellwied, June 30, 2002 Tracking efficiencies LD vs. SD • Tracking efficiencies: • For 100% hit efficiency: (95.3±0.13)% • For 98% hit efficiency: (94.5±0.14)% • For 90% hit efficiency: (89.5±0.20)% •  LD  SD Tracking efficiencies: • For 100% hit efficiency: (97.3±0.10)% • For 98% hit efficiency: (96.6±0.12)% • For 90% hit efficiency: (92.7±0.16)%

  13. With the maximum of d3p distribution at ~(1.5-2)10-3, the data are consistent with the earlier momentum resolution simulations (B. Schumm, VR, et al): within a factor of ~2 in the momentum range of 0.5 GeV/c < pT < 20 GeV/c. V. L. Rykov, June 28, 2002 Momentum studies (LD / SD) log10(Pt, GeV/c) SD log10(Pt, GeV/c) LD

  14. R.Bellwied, June 30, 2002 Missing and ghost energies • For hit efficiency 100%: • Missing energy = (11.7±0.6) GeV = (7.1±0.3)% • Ghost energy = (19.6±0.8) GeV • = (13.1±0.6)% •  LD  SD For hit efficiency 100%: • Missing energy = (5.7±0.4) GeV = (3.3±0.2)% • Ghost energy = (4.8±0.4) GeV = (2.9±0.2)%

  15. With the maximum of d3p distribution at ~(1.5-2)10-3, the data are consistent with the earlier momentum resolution simulations (B. Schumm, VR, et al): within a factor of ~2 in the momentum range of 0.5 GeV/c < pT < 20 GeV/c. R.Bellwied, June 30, 2002 Preliminary conclusions • Momentum resolution • The SD option has slightly better resolution at high momentum and slightly worse resolution at low momentum compared to LD • With the existing 3d tracking and pattern recognition software (Mike Ronan et al.) the SD option has a slight advantage in tracking efficiency, shows less missing and ghost energy, and less ghost tracks)

  16. time TrainorRf-pulse For NLC/JLC, it is expected ~2.2 hadronic -events per train, in addition to the trigger, with the average number of tracks ~17 and energy deposit in the calorimeter ~100 GeV per such an event. T. Abe et al, Physics Resource Book for Snowmass 2001 and ref. therein Track Timing at e+e- Linear Collider with the Silicon Drift Detector Main TrackerR. Bellwied, D. Cinabro, V. L. RykovWayne State University,Detroit, Michigan Chicago LC Workshop, Chicago, Illinois, January 7-9, 2002V. L. Rykov, Wayne State University

  17. Conclusion of track-timing study(hep-ex/0202030, submitted to NIM) • It is shown that, with the SDD based central Main Tracker for the detector at e+e- Linear Collider, the track selection and timing is possible at the nanosecond and even sub-nanosecond level. • This means that, even at the NLC and/or JLC with the bunch spacing at 1.4 ns, each high-PT track can be assigned to a particular bunch crossing at the confidential level of up to ~2. • For the considered here 5-layer central Main Tracker, it is suggested to make layers1, 2, 3 and 5 drifting along z-axis, but layer 4 drifting along the azimuth (-axis) with effectively no negative impact on the tracker’s momentum resolution. In other words, all the above is just for free with the SDD Main Tracker. Chicago LC Workshop, Chicago, Illinois, January 7-9, 2002V. L. Rykov, Wayne State University

  18. Improve position resolution to 5mm Decrease anode pitch from 250 to 100mm. Stiffen resistor chain and drift faster. Improve radiation length Reduce wafer thickness from 300mm to 150mm Move FEE to edges or change from hybrid to SVX Air cooling vs. water cooling Use 6in instead of 4in Silicon wafers to reduce #channels. More extensive radiation damage studies. Detectors/FEE can withstand around 100 krad (g,n) PASA is BIPOLAR (intrinsically rad. hard.) SCA can be produced in rad. hard process. R.Bellwied, June 30, 2002 R&D for Large Tracker Application

  19. R.Bellwied, June 30, 2002 WSU R&D interests • Main goal: develop either full scale tracker or intermediate tracking layer on the basis of Silicon Drift technology. • Projects: Hardware • 1.) design new prototype drift detector layout (incl. frontend stage) optimized for LC use (i.e. larger detector, higher pitch, higher voltage, less power consumption) • 2.) collaborate with BNL on prototype production of wafer and frontend chip Software • 1.) optimize 3d tracking code for solid state tracker, compare performance to gas detector and other silicon technologies • 2.) write slow simulator for detector response and apply STAR tracking and pattern recognition • 3.) find unique drift detector applications (e.g. track timing)

  20. R.Bellwied, June 30, 2002 WSU proposal for the next 3 years (~50 K per project per year) In collaboration with the Instrumentation division at BNL: 1.) design and produce a prototype batch (~20) of new, optimized Silicon drift detectors. The proposed major changes compared to the old STAR design are: a.) increase the detector size by using six inch rather than four inch wafers b.) increase the readout pitch in order to reduce the channel count c.)  thin the wafer from 300 micron to 150 micron d.) operate wafers at higher voltage (up to 2500 V) to accommodate new drift length 2.) design and produce a new prototype of a CMOS based frontend chip. a.)    use deep sub-micron technology to improve radiation hardness b.)    reduce power consumption to allow air-cooling of the detector c.)    potentially include the ADC stage into the PASA/SCA design d.)    test tape automated bonding rather than wire-bonding 

  21. R.Bellwied, June 30, 2002 WSU proposal (cont.) 3.) we also propose to investigate a design for the mechanical support of the Silicon ladders based on a design used for the Silicon Strip detector layer in STAR.   4.)software efforts a.)continue our comparative study of the performance of a Silicon drift detector based main tracker with the existing tracking and pattern recognition code... b.)provide a full GEANT based geometry definition of our proposed tracker before the fall of 2002. c.)port a detector response code from STAR into the LC simulation framework. d.)adapt a code recently written by a WSU led software group for STAR which allows track matching between the two main tracking detectors in STAR and the electro-magnetic calorimeter in STAR. An integrated tracking code (IT) can be applied to the SD design in order to simultaneously analyze the information from the vertex detector, the main tracker and the calorimeter.

  22. R.Bellwied, June 30, 2002 What’s next for SDD ? • The project has to grow, we need more groups interested in SDD (as of now only WSU and BNL expressed some interest). • Prototype detectors for use in test setups at universities or other National Labs are available through WSU/BNL. • People with mask design skills could work on new prototype layouts. • The wafer and frontend electronics R&D could be split in two projects. • What should the frontend be: DSM-CMOS, bipolar, different chips for different stages or single chip, implanted or wire-bonded ? • Readout electronics and DAQ integration have not been addressed at all. • Software development and simulations needs a lot more manpower. Talk to us if you’re interested (bellwied@physics.wayne.edu) • Check out the web at: http://rhic15.physics.wayne.edu/~bellwied/nlc

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