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Chapter 5 Memory

Chapter 5 Memory. Introduction. Embedded system’s functionality aspects Processing processors transformation of data Storage memory retention of data Communication buses transfer of data. m × n memory. …. m words. …. n bits per word. memory external view. r/w.

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Chapter 5 Memory

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  1. Chapter 5 Memory

  2. Introduction • Embedded system’s functionality aspects • Processing • processors • transformation of data • Storage • memory • retention of data • Communication • buses • transfer of data

  3. m × n memory … m words … n bits per word memory external view r/w 2k × n read and write memory enable A0 … Ak-1 … Qn-1 Q0 Memory: basic concepts • Stores large number of bits • m x n: m words of n bits each • k = Log2(m) address input signals • or m = 2^k words • e.g., 4,096 x 8 memory: • 32,768 bits • 12 address input signals • 8 input/output data signals • Memory access • r/w: selects read or write • enable: read or write only when asserted • multiport: multiple accesses to different locations simultaneously

  4. permanence Storage Mask-programmed ROM Ideal memory OTP ROM Life of product EPROM Tens of EEPROM FLASH years Battery NVRAM Nonvolatile life (10 years) In-system SRAM/DRAM programmable Near Write zero ability During External External External External In-system, fast fabrication programmer, programmer, programmer programmer writes, 1,000s OR in-system, OR in-system, only one time only unlimited 1,000s block-oriented of cycles cycles writes, 1,000s of cycles of cycles Write ability and storage permanence of memories, showing relative degrees along each axis (not to scale). Write ability/ storage permanence • Traditional ROM/RAM distinctions • ROM • read only, bits stored without power • RAM • read and write, lose stored bits without power • Traditional distinctions blurred • Advanced ROMs can be written to • e.g., EEPROM • Advanced RAMs can hold bits without power • e.g., NVRAM • Write ability • Manner and speed a memory can be written • Storage permanence • ability of memory to hold stored bits after they are written

  5. Write ability • Ranges of write ability • High end • processor writes to memory simply and quickly • e.g., RAM • Middle range • processor writes to memory, but slower • e.g., FLASH, EEPROM • Lower range • special equipment, “programmer”, must be used to write to memory • e.g., EPROM, OTP ROM • Low end • bits stored only during fabrication • e.g., Mask-programmed ROM • In-system programmable memory • Can be written to by a processor in the embedded system using the memory • Memories in high end and middle range of write ability

  6. Storage permanence • Range of storage permanence • High end • essentially never loses bits • e.g., mask-programmed ROM • Middle range • holds bits days, months, or years after memory’s power source turned off • e.g., NVRAM • Lower range • holds bits as long as power supplied to memory • e.g., SRAM • Low end • begins to lose bits almost immediately after written • e.g., DRAM • Nonvolatile memory • Holds bits after power is no longer supplied • High end and middle range of storage permanence

  7. External view 2k × n ROM enable A0 … Ak-1 … Qn-1 Q0 ROM: “Read-Only” Memory • Nonvolatile memory • Can be read from but not written to, by a processor in an embedded system • Traditionally written to, “programmed”, before inserting to embedded system • Uses • Store software program for general-purpose processor • program instructions can be one or more ROM words • Store constant data needed by system • Implement combinational circuit

  8. Internal view 8 × 4 ROM word 0 3×8decoder enable word 1 word 2 A0 word line A1 A2 data line programmable connection wired-OR Q3 Q2 Q1 Q0 Example: 8 x 4 ROM • Horizontal lines = words • Vertical lines = data • Lines connected only at circles • Decoder sets word 2’s line to 1 if address input is 010 • Data lines Q3 and Q1 are set to 1 because there is a “programmed” connection with word 2’s line • Word 2 is not connected with data lines Q2 and Q0 • Output is 1010

  9. Mask-programmed ROM • Connections “programmed” at fabrication • set of masks • Lowest write ability • only once • Highest storage permanence • bits never change unless damaged • Typically used for final design of high-volume systems • spread out NRE cost for a low unit cost

  10. OTP ROM: One-time programmable ROM • Connections “programmed” after manufacture by user • user provides file of desired contents of ROM • file input to machine called ROM programmer • each programmable connection is a fuse • ROM programmer blows fuses where connections should not exist • Very low write ability • typically written only once and requires ROM programmer device • Very high storage permanence • bits don’t change unless reconnected to programmer and more fuses blown • Commonly used in final products • cheaper, harder to inadvertently modify

  11. 0V floating gate drain source (a) +15V source drain (b) 5-30 min drain source (c) (d) EPROM: Erasable programmable ROM • Programmable component is a MOS transistor • Transistor has “floating” gate surrounded by an insulator • (a) Negative charges form a channel between source and drain storing a logic 1 • (b) Large positive voltage at gate causes negative charges to move out of channel and get trapped in floating gate storing a logic 0 • (c) (Erase) Shining UV rays on surface of floating-gate causes negative charges to return to channel from floating gate restoring the logic 1 • (d) An EPROM package showing quartz window through which UV light can pass • Better write ability • can be erased and reprogrammed thousands of times • Reduced storage permanence • program lasts about 10 years but is susceptible to radiation and electric noise • Typically used during design development .

  12. EEPROM: Electrically erasable programmable ROM • Programmed and erased electronically • typically by using higher than normal voltage • can program and erase individual words • Better write ability • can be in-system programmable with built-in circuit to provide higher than normal voltage • built-in memory controller commonly used to hide details from memory user • writes very slow due to erasing and programming • “busy” pin indicates to processor EEPROM still writing • can be erased and programmed tens of thousands of times • Similar storage permanence to EPROM (about 10 years) • Far more convenient than EPROMs, but more expensive

  13. Flash Memory • Extension of EEPROM • Same floating gate principle • Same write ability and storage permanence • Fast erase • Large blocks of memory erased at once, rather than one word at a time • Blocks typically several thousand bytes large • Writes to single words may be slower • Entire block must be read, word updated, then entire block written back • Used with embedded systems storing large data items in nonvolatile memory • e.g., digital cameras, TV set-top boxes, cell phones

  14. internal view I3 I2 I1 I0 external view r/w 2k × n read and write memory 4×4 RAM enable 2×4 decoder enable A0 … A0 A1 Ak-1 Memory cell … rd/wr To every cell Qn-1 Q0 Q3 Q2 Q1 Q0 RAM: “Random-access” memory • Typically volatile memory • bits are not held without power supply • Read and written to easily by embedded system during execution • Internal structure more complex than ROM • a word consists of several memory cells, each storing 1 bit • each input and output data line connects to each cell in its column • rd/wr connected to every cell • when row is enabled by decoder, each cell has logic that stores input data bit when rd/wr indicates write or outputs stored bit when rd/wr indicates read

  15. SRAM Data' Data W DRAM Data W Basic types of RAM • SRAM: Static RAM • Memory cell uses flip-flop to store bit • Requires 6 transistors • Holds data as long as power supplied • DRAM: Dynamic RAM • Memory cell uses MOS transistor and capacitor to store bit • More compact than SRAM • “Refresh” required due to capacitor leak • word’s cells refreshed when read • Typical refresh rate 15.625 microsec. • Slower to access than SRAM memory cell internals

  16. SRAM

  17. DRAM

  18. Ram variations • PSRAM: Pseudo-static RAM • DRAM with built-in memory refresh controller • Popular low-cost high-density alternative to SRAM • NVRAM: Nonvolatile RAM • Holds data after external power removed • Battery-backed RAM • SRAM with own permanently connected battery • writes as fast as reads • no limit on number of writes unlike nonvolatile ROM-based memory • SRAM with EEPROM or flash • stores complete RAM contents on EEPROM or flash before power turned off

  19. rd'/wr Processor Memory enable addr[0-11] data[0-7] bus bus structure A simple bus • Wires: • Uni-directional or bi-directional • One line may represent multiple wires • Bus • Set of wires with a single function • Address bus, data bus • Or, entire collection of wires • Address, data and control • Associated protocol: rules for communication

  20. rd'/wr Processor Memory port enable addr[0-11] data[0-7] Ports • Conducting device on periphery • Connects bus to processor or memory • Often referred to as a pin • Actual pins on periphery of IC package that plug into socket on printed-circuit board • Sometimes metallic balls instead of pins • Today, metal “pads” connecting processors and memories within single IC • Single wire or set of wires with single function • E.g., 12-wire address port bus

  21. rd'/wr enable addr data tsetup tread read protocol rd'/wr enable addr data tsetup twrite write protocol Timing Diagrams • Most common method for describing a communication protocol • Time proceeds to the right on x-axis • Control signal: low or high • May be active low (e.g., go’, /go, or go_L) • Use terms assert (active) and deassert • Asserting go’ means go=0 • Data signal: not valid or valid • Protocol may have subprotocols • Called bus cycle, e.g., read and write • Each may be several clock cycles • Read example • rd’/wr set low,address placed on addr for at least tsetup time before enable asserted, enable triggers memory to place data on data wires by time tread

  22. RAM timing diagrams

  23. Time-multiplexed data transfer Master Servant Master Servant req req 7:0 15:8 data(15:0) data(15:0) addr data addr data mux demux mux demux data(8) addr/data req req data addr/data data serializing address/data muxing addr data Basic protocol concepts • Actor: master initiates, servant (slave) respond • Direction: sender, receiver • Addresses: special kind of data • Specifies a location in memory, a peripheral, or a register within a peripheral • Time multiplexing • Share a single set of wires for multiple pieces of data • Saves wires at expense of time

  24. Master Servant Master req Servant req ack data data req 1 3 req 1 3 ack 2 4 data 2 4 data taccess 1. Master asserts req to receive data 1. Master asserts req to receive data 2. Servant puts data on bus within time taccess 2. Servant puts data on bus and asserts ack 3. Master receives data and deasserts req 3. Master receives data and deasserts req 4. Servant ready for next request 4. Servant ready for next request Strobe protocol Handshake protocol Basic protocol concepts: control methods

  25. Memory Interface No common clock between CPU and memory Follow asynchronous 4-cycle handshake request/wait (ack) protocol 1. Request Asserted 2. Wait Unasserted 3. Request Unasserted 4. Wait Asserted Read Cycle Write Cycle Memory cannot make request unless Wait signal is asserted Hi-to-Lo transition on Wait implies that data is ready (read) or data has been latched by memory (write)

  26. Master Servant req wait data req 1 3 req 1 4 wait wait 2 3 data 2 4 data 5 taccess taccess 1. Master asserts req to receive data 1. Master asserts req to receive data 2. Servant puts data on buswithin time taccess 2. Servant can't put data within taccess, asserts wait ack (wait line is unused) 3. Servant puts data on bus and deasserts wait 3. Master receives data and deasserts req 4. Master receives data and deasserts req 4. Servant ready for next request 5. Servant ready for next request Fast-response case Slow-response case A strobe/handshake compromise

  27. Microprocessor interfacing: I/O addressing • A microprocessor communicates with other devices using some of its pins • Port-based I/O (parallel I/O) • Processor has one or more N-bit ports • Processor’s software reads and writes a port just like a register • E.g., P0 = 0xFF; v = P1.2; -- P0 and P1 are 8-bit ports • Bus-based I/O • Processor has address, data and control ports that form a single bus • Communication protocol is built into the processor • A single instruction carries out the read or write protocol on the bus

  28. Processor Memory Processor Port 0 Port 1 Port 2 System bus Port 3 Parallel I/O peripheral Parallel I/O peripheral Port A Port B Port C Port A Port B Port C Adding parallel I/O to a bus-based I/O processor Extended parallel I/O Compromises/extensions • Parallel I/O peripheral • When processor only supports bus-based I/O but parallel I/O needed • Each port on peripheral connected to a register within peripheral that is read/written by the processor • Extended parallel I/O • When processor supports port-based I/O but more ports needed • One or more processor ports interface with parallel I/O peripheral extending total number of ports available for I/O • e.g., extending 4 ports to 6 ports in figure

  29. Types of bus-based I/O: memory-mapped I/O and standard I/O • Processor talks to both memory and peripherals using same bus – two ways to talk to peripherals • Memory-mapped I/O • Peripheral registers occupy addresses in same address space as memory • e.g., Bus has 16-bit address • lower 32K addresses may correspond to memory • upper 32k addresses may correspond to peripherals • Standard I/O (I/O-mapped I/O) • Additional pin (M/IO) on bus indicates whether a memory or peripheral access • e.g., Bus has 16-bit address • all 64K addresses correspond to memory when M/IO set to 0 • all 64K addresses correspond to peripherals when M/IO set to 1

  30. Memory-mapped I/O vs. Standard I/O • Memory-mapped I/O • Requires no special instructions • Assembly instructions involving memory like MOV and ADD work with peripherals as well • Standard I/O requires special instructions (e.g., IN, OUT) to move data between peripheral registers and memory • Standard I/O • No loss of memory addresses to peripherals • Simpler address decoding logic in peripherals possible • When number of peripherals much smaller than address space then high-order address bits can be ignored • smaller and/or faster comparators

  31. Microprocessor interfacing: interrupts • Suppose a peripheral intermittently receives data, which must be serviced by the processor • The processor can poll the peripheral regularly to see if data has arrived – wasteful • The peripheral can interrupt the processor when it has data • Requires an extra pin or pins: Int • If Int is 1, processor suspends current program, jumps to an Interrupt Service Routine, or ISR • Known as interrupt-driven I/O • Essentially, “polling” of the interrupt pin is built-into the hardware, so no extra time!

  32. Microprocessor interfacing: interrupts • What is the address (interrupt address vector) of the ISR? • Fixed interrupt • Address built into microprocessor, cannot be changed • Either ISR stored at address or a jump to actual ISR stored if not enough bytes available • Vectored interrupt • Peripheral must provide the address • Common when microprocessor has multiple peripherals connected by a system bus • Compromise: interrupt address table

  33. 1(a): μP is executing its main program. 1(b): P1 receives input data in a register with address 0x8000. Time 2: P1 asserts Int to request servicing by the microprocessor. 3: After completing instruction at 100, μP sees Int asserted, saves the PC’s value of 100, and sets PC to the ISR fixed location of 16. 4(a): The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x8001. 4(b): After being read, P1 de-asserts Int. 5: The ISR returns, thus restoring PC to 100+1=101, where μP resumes executing. Interrupt-driven I/O using fixed ISR location

  34. μP Data memory Program memory ISR 16: MOV R0, 0x8000 System bus 17: # modifies R0 18: MOV 0x8001, R0 19: RETI # ISR return ... P1 P2 Int Main program ... PC 0x8000 0x8001 100: instruction 101: instruction Interrupt-driven I/O using fixed ISR location 1(a): P is executing its main program 1(b): P1 receives input data in a register with address 0x8000.

  35. μP Data memory Program memory ISR 16: MOV R0, 0x8000 System bus 17: # modifies R0 18: MOV 0x8001, R0 19: RETI # ISR return ... P1 P2 Int Main program 1 ... PC 0x8000 0x8001 100: instruction 101: instruction Interrupt-driven I/O using fixed ISR location 2: P1 asserts Int to request servicing by the microprocessor Int

  36. μP Data memory Program memory ISR 16: MOV R0, 0x8000 System bus 17: # modifies R0 18: MOV 0x8001, R0 19: RETI # ISR return ... P1 P2 Int Main program ... PC 0x8000 0x8001 100: instruction 100 100 101: instruction Interrupt-driven I/O using fixed ISR location 3: After completing instruction at 100, P sees Int asserted, saves the PC’s value of 100, and sets PC to the ISR fixed location of 16.

  37. μP Data memory Program memory ISR 16: MOV R0, 0x8000 System bus System bus 17: # modifies R0 18: MOV 0x8001, R0 19: RETI # ISR return ... P1 P1 P1 P2 P2 Int Int Main program 0 ... PC 0x8000 0x8001 0x8001 100: instruction 101: instruction 0x8000 Interrupt-driven I/O using fixed ISR location 4(a): The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x8001. 4(b): After being read, P1 deasserts Int. 100

  38. μP Data memory Program memory ISR ISR 16: MOV R0, 0x8000 System bus 16: MOV R0, 0x8000 17: # modifies R0 17: # modifies R0 18: MOV 0x8001, R0 18: MOV 0x8001, R0 19: RETI # ISR return ... 19: RETI # ISR return P1 P2 Int ... Main program ... Main program PC 0x8000 0x8001 ... 100: instruction +1 100: instruction 100 100 100 101: instruction 101: instruction Interrupt-driven I/O using fixed ISR location 5: The ISR returns, thus restoring PC to 100+1=101, where P resumes executing.

  39. 1(a): μP is executing its main program. 1(b): P1 receives input data in a register with address 0x8000. Time 2: P1 asserts Int to request servicing by the microprocessor. 3: After completing instruction at 100, μP sees Int asserted, saves the PC’s value of 100, and asserts Inta. 4: P1 detects Inta and puts interrupt address vector 16 on the data bus. 5(a):μP jumps to the address on the bus (16). The ISR there reads data from 0x8000, modifies the data, and writes the resulting data to 0x8001. 5(b): After being read, P1 deasserts Int. 6: The ISR returns, thus restoring PC to 100+1=101, where μP resumes executing. Interrupt-driven I/O using vectored interrupt

  40. μP Data memory Program memory ISR 16: MOV R0, 0x8000 System bus 17: # modifies R0 18: MOV 0x8001, R0 19: RETI # ISR return ... P1 P2 Inta Main program Int 16 ... PC 100: instruction 0x8000 0x8001 100 101: instruction Interrupt-driven I/O using vectored interrupt 1(a): P is executing its main program 1(b): P1 receives input data in a register with address 0x8000.

  41. μP Data memory Program memory ISR 16: MOV R0, 0x8000 System bus 17: # modifies R0 18: MOV 0x8001, R0 19: RETI # ISR return ... Inta P1 P2 Int Main program 16 ... 1 PC 100: instruction 0x8000 0x8001 100 101: instruction Interrupt-driven I/O using vectored interrupt 2: P1 asserts Int to request servicing by the microprocessor Int

  42. μP Data memory Program memory ISR 16: MOV R0, 0x8000 System bus 17: # modifies R0 18: MOV 0x8001, R0 19: RETI # ISR return 1 ... Inta Inta P1 P2 Int Main program 16 ... PC 100: instruction 0x8000 0x8001 100 100 101: instruction Interrupt-driven I/O using vectored interrupt 3: After completing instruction at 100, μP sees Int asserted, saves the PC’s value of 100, and asserts Inta

  43. μP Data memory Program memory ISR 16: MOV R0, 0x8000 System bus System bus 17: # modifies R0 16 18: MOV 0x8001, R0 19: RETI # ISR return ... Inta P1 P2 Int Main program 16 16 ... PC 100: instruction 0x8000 0x8001 101: instruction Interrupt-driven I/O using vectored interrupt 4: P1 detects Inta and puts interrupt address vector 16 on the data bus 100

  44. μP Data memory Program memory ISR ISR 16: MOV R0, 0x8000 System bus System bus 16: MOV R0, 0x8000 17: # modifies R0 17: # modifies R0 18: MOV 0x8001, R0 18: MOV 0x8001, R0 19: RETI # ISR return ... 19: Inta RETI # ISR return P1 P1 P2 P2 ... Int Int Main program 16 ... Main program 0 PC ... 100: instruction 0x8000 0x8000 0x8001 0x8001 100: instruction 100 101: instruction 101: instruction Interrupt-driven I/O using vectored interrupt 5(a): PC jumps to the address on the bus (16). The ISR there reads data from 0x8000, modifies the data, and writes the resulting data to 0x8001. 5(b): After being read, P1 deasserts Int.

  45. μP Data memory Program memory ISR ISR 16: MOV R0, 0x8000 System bus 16: MOV R0, 0x8000 17: # modifies R0 17: # modifies R0 18: MOV 0x8001, R0 18: MOV 0x8001, R0 19: RETI # ISR return ... 19: RETI # ISR return P1 P2 Int ... Main program ... Main program PC 0x8000 0x8001 ... 100: instruction +1 100: instruction 100 100 100 101: instruction 101: instruction Interrupt-driven I/O using vectored interrupt 6: The ISR returns, thus restoring the PC to 100+1=101, where the μP resumes

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