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Understanding Network Switches and Routers: Functionality and Architecture

Learn about the structure, functionality, and architecture of network switches and routers, including how packets are processed, header lookup, addressing and lookup, interconnect options, and different router designs.

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Understanding Network Switches and Routers: Functionality and Architecture

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  1. 15-441 Computer Networks Switching Professor Hui Zhang hzhang@cs.cmu.edu

  2. Switches circuit switch Ethernet switch ATM switch IP router Switch fabric high capacity interconnect Line card address lookup in the data path (forwarding) Control Processor load the forwarding table (routing or signaling) Control Processor Switch Fabric Line Cards Line Cards Structure of A Generic Communication Switch

  3. Switches/Routers • Control plane: how forwarding tables are computed • Router: routing protocols • Ethernet switch: learning and spanning tree • Data plane: how each packet is processed? • Header lookup and forward the packet to right output port • Manage buffer and bandwidth resource

  4. Flat address Ethernet: 48 bit MAC address ATM: 28 bit VPI/VCI DS-0: timeslot location Limited scalability High speed lookup Hierarchical address IP <network>.<subnet>.<host> Telephone: country.area.home Scalable Easy lookup if boundary is fixed telephony Difficult lookup if boundary is flexible longest prefix match for IP Addressing and Look-up

  5. Input and output interfaces are connected through an interconnect A interconnect can be implemented by Shared memory Low capacity routers (e.g., PC-based routers) Shared bus Medium capacity routers Point-to-point (switched) bus High capacity routers Generic Architecture input interface output interface Inter- connect

  6. CPU Buffer Memory Route Table CPU Line Interface Line Interface Line Interface Memory MAC MAC MAC Shared Memory (1st Generation) Shared Backplane Line Interface Typically < 0.5Gbps aggregate capacity Limited by rate of shared memory (* Slide by Nick McKeown)

  7. CPU Buffer Memory Route Table Line Card Line Card Line Card Buffer Memory Buffer Memory Buffer Memory Fwding Cache Fwding Cache Fwding Cache MAC MAC MAC Shared Bus (2nd Generation) Typically < 5Gb/s aggregate capacity; Limited by shared bus (* Slide by Nick McKeown)

  8. Switched Backplane Line Card CPU Card Line Card Local Buffer Memory Local Buffer Memory Line Interface CPU Routing Table Memory Fwding Table Fwding Table MAC MAC Point-to-Point Switch (3rd Generation) Typically < 50Gbps aggregate capacity (*Slide by Nick McKeown)

  9. What a Router Looks Like Cisco GSR 12416 Juniper M160 19” 19” Capacity: 160Gb/sPower: 4.2kW Capacity: 80Gb/sPower: 2.6kW 3ft 6ft 2ft 2.5ft Slide by Nick McKeown

  10. Interconnect • Point-to-point switch allows to simultaneously transfer a packet between any two disjoint pairs of input-output interfaces • Goal: come-up with a schedule that • Provide Quality of Service • Maximize router throughput • Challenges: • Address head-of-line blocking at inputs • Resolve input/output speedups contention • Avoid packet dropping at output if possible • Note: packets are fragmented in fix sized cells at inputs and reassembled at outputs

  11. Output Queued Routers • Only output interfaces store packets • Advantages • Easy to design algorithms: only one congestion point • Disadvantages • Requires an output speedup of N, where N is the number of interfaces  not feasible input interface output interface Backplane RO C

  12. Input Queued Routers • Only input interfaces store packets • Advantages • Easy to built • Store packets at inputs if contention at outputs • Relatively easy to design algorithms • Only one congestion point, but not output… • need to implement backpressure • Disadvantages • Hard to achieve utilization  1 (due to output contention, head-of-line blocking) • However, theoretical and simulation results show that for realistic traffic an input/output speedup of 2 is enough to achieve utilizations close to 1 input interface output interface Backplane RO C

  13. Cannot be transferred because is blocked by red cell Cannot be transferred because output buffer overflow Head-of-line Blocking • The cell at the head of an input queue cannot be transferred, thus blocking the following cells Input 1 Output 1 Input 2 Output 2 Input 3 Output 3

  14. A Router with Input QueuesHead of Line Blocking The best that any queueing system can achieve. Slide by Nick McKeown

  15. Solution to Avoid Head-of-line Blocking • Maintain at each input N virtual queues, i.e., one per output Input 1 Output 1 Output 2 Input 2 Output 3 Input 3

  16. Combined Input-Output Queued (CIOQ) Routers • Both input and output interfaces store packets • Advantages • Easy to built • Utilization 1 can be achieved with limited input/output speedup (<= 2) • Disadvantages • Harder to design algorithms • Two congestion points • Need to design flow control input interface output interface Backplane RO C

  17. Input Interface • Packet forwarding: decide to which output interface to forward each packet based on the information in packet header • Examine packet header • Lookup in forwarding table • Update packet header input interface output interface Inter- connect

  18. Lookup • Identify the output interface to forward an incoming packet based on packet’s destination address • Routing tables summarize information by maintaining a mapping between IP address prefixes and output interfaces • How are routing tables computed? • Route lookup  find the longest prefix in the table that matches the packet destination address

  19. 12.82.100.101 128.16.120.111 IP Routing • Packet with destination address 12.82.100.101 is sent to interface 2, as 12.82.100.xxx is the longest prefix matching packet’s destination address 128.16.120.xxx 1 12.82.xxx.xxx 3 12.82.100.xxx 2 … … 1 2

  20. Patricia Tries • Use binary tree paths to encode prefixes • Advantage: simple to implement • Disadvantage: one lookup may take O(m), where m is number of bits (32 in the case of IPv4) 1 0 001xx 2 0100x 3 10xxx 1 01100 5 1 0 0 1 0 1 1 2 0 0 3 0 5

  21. Flat address Ethernet: 48 bit MAC address ATM: 28 bit VPI/VCI DS-0: timeslot location Limited scalability High speed lookup Hierarchical address IP <network>.<subnet>.<host> Telephone: country.area.home Scalable Easy lookup if boundary is fixed telephony Difficult lookup if boundary is flexible longest prefix match for IP Addressing and Look-up

  22. Output Functions • Buffer management: decide when and which packet to drop • Scheduler: decide when and which packet to transmit Buffer Scheduler 1 2

  23. Example: FIFO router • Most of today’s routers • Drop-tail buffer management: when buffer is full drop the incoming packet • First-In-First-Out (FIFO) Scheduling: schedule packets in the same order they arrive

  24. Output Functions (cont’d) • Packet classification: map each packet to a predefined flow/connection (for datagram forwarding) • Use to implement more sophisticated services (e.g., QoS) • Flow: a subset of packets between any two endpoints in the network flow 1 Classifier flow 2 Scheduler 1 2 flow n Buffer management

  25. Packet Classification • Classify an IP packet based on a number of fields in the packet header, e.g., • source/destination IP address (32 bits) • source/destination port number (16 bits) • Type of service (TOS) byte (8 bits) • Type of protocol (8 bits) • In general fields are specified by range flow 1 flow 2 Classifier Scheduler 1 flow n 2 Buffer management

  26. Example of Classification Rules • Access-control in firewalls • Deny all e-mail traffic from ISP-X to Y • Policy-based routing • Route IP telephony traffic from X to Y via ATM • Differentiate quality of service • Ensure that no more than 50 Mbps are injected from ISP-X

  27. Scheduler • One FIFO queue per flow • Scheduler decides when and from which queue to send a packet • Goals of a scheduler: • Quality of service • Protection (stop a flow from hogging the entire output link) • Fast! flow 1 flow 2 Classifier Scheduler 1 flow n 2 Buffer management

  28. Example: Priority Scheduler • Priority scheduler: packets in the highest priority queue are always served before the packets in lower priority queues High priority Medium priority Priority Scheduler Low priority

  29. Example: Round Robin Scheduler • Round robin: packets are served in a round-robin fashion High priority Medium priority Priority Scheduler Low priority

  30. Another Forwarding Technique: Source Routing • Each packet specifies the sequence of routers, or alternatively the sequence of output ports, from source to destination source 1 1 2 2 1 1 3 3 2 2 4 4 3 3 4 4 4 3 4 1 1 2 2 4 3 4 3 3 4 3 4 4 4

  31. Source Routing (cont’d) • Gives the source control of the path • Not scalable • Packet overhead proportional to the number of routers • Typically, require variable header length which is harder to implement • Hard for source to have complete information • Loose source routing  sender specifies only a subset of routers along the path

  32. Concepts • Control plane vs. data plane • Various switching architectures • Buffering • Input vs. Output vs. Combined Input/Output • Head of line blocking • Scheduling • Header lookup

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