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CERC Front End FPGA Development Progress Report by Osman Zorba

CERC Front End FPGA Development Progress Report by Osman Zorba. O. Zorba CALICE 11/03/2004. Overview. VFE-PCB Interface Specification (August 2003) was found to be incorrect. VFE signals had to be modified to accommodate the new timing.

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CERC Front End FPGA Development Progress Report by Osman Zorba

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  1. CERC Front End FPGA Development Progress Reportby Osman Zorba O. Zorba CALICE 11/03/2004 © Imperial College London

  2. Overview • VFE-PCB Interface Specification (August 2003) was found to be incorrect. VFE signals had to be modified to accommodate the new timing. • Further DAC tests has shown that some of the DAC bits get corrupted. DAC code has been investigated the code has been modified to allow more time for DAC data to settle. • Compact Flash has been programmed with the latest code to allow all channels to be tested. One of the FE6 DACs is not working. • Slice utilisation with FED Serial code has been investigated. O. Zorba CALICE 11/03/2004 © Imperial College London

  3. VFE Signals • VFE-PCB Interface Specification (August 2003) is incorrect. • The VFE HOLD signal should have been inverted. The HOLD signal has been modified and in the current FE-FPGA code is programmable. • The number of VFE MUXCLKs should have been 36 and NOT 18. • SROUT pulse does not stay high during the last VFE MUXCLK only. SROUT goes to high on the rising edge of the last (36th) MUXCLK and goes to low on the next MUXCLK. O. Zorba CALICE 11/03/2004 © Imperial College London

  4. VFE Signals – Measurements #1 1.Trigger 2. VFE HOLD 3. RESET 4. MUXCLK O. Zorba CALICE 11/03/2004 © Imperial College London

  5. VFE Signals – Measurements #2Trigger to HOLD Delay 1.Trigger 2. VFE HOLD 3. RESET 4. MUXCLK O. Zorba CALICE 11/03/2004 © Imperial College London

  6. VFE Signals – Measurements #3Trigger to TCALIB 1.TCALIB 3. Trigger 4. HOLD O. Zorba CALICE 11/03/2004 © Imperial College London

  7. VFE Signals – Measurements #4Trigger from Dev Board 2. Trigger 3. Trigger on SCSI 4. HOLD O. Zorba CALICE 11/03/2004 © Imperial College London

  8. VFE Signals – Measurements #5Signals to and from VFE 1. HOLD 2. SROUT 3. VFE VOUT 4. MUXCLK O. Zorba CALICE 11/03/2004 © Imperial College London

  9. DAC Test Results #1 O. Zorba CALICE 11/03/2004 © Imperial College London

  10. DAC Test Results #2 O. Zorba CALICE 11/03/2004 © Imperial College London

  11. FPGA Utilisation O. Zorba CALICE 11/03/2004 © Imperial College London

  12. Future Work • Further testing of VFE Control Logic. • Investigate and resolve the BUSY signal during the first 12 set of data. • Complete the LINKARRAY code integration. • Investigate the implications of controlling the ADC’s separately. O. Zorba CALICE 11/03/2004 © Imperial College London

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