Charu Nagpal Rajesh Garg Sunil P. Khatri Department of Electrical and Computer Engineering,

1. A Delay-efficient Radiation-hard Digital Design ApproachUsing Code Word State Preserving (CWSP) Elements Charu Nagpal Rajesh Garg Sunil P. Khatri Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX

2. Outline • Motivation and Introduction • Previous Work • Nicolaidis et. al. (CWSP based) • Our Approach • System Level • Circuit Level • Radiation protection analysis • Maximum glitch width • Experimental Results • Conclusions and Future Work

3. Why radiation-hardening? • Historically mainly used for space and military electronics • Higher levels of radiation in space and combat environments • Terrestrial electronics also becoming vulnerable • Shrinking feature size and supply voltage • Reduced capacitances means less charge is required to flip node voltage • This has resulted in a renewed interest in radiation-hardened circuit design

4. Effects of radiation particle strike • Neutrons, protons and heavy cosmic ions • Ions strike diffusion regions • Deposit charge • Result in voltage spike at the output of a gate • This can flip the state of a memory cell (SEU) • For a combinational gate, this spike (SET) may cause an incorrect value to be sampled by the latches or flip-flops of the design

5. Modeling a radiation-strike • Charge deposited (Q) at a node is given by where: Lis Linear Energy Transfer (MeV-cm2/mg) t is the depth of the collection volume (µm) • The resulting current pulse is traditionally described as where: ta is the collection time constant tb is the ion track establishment constant (Q=100fC, ta= 200ps and tb= 50ps) Iseu (µA) time (ns)

6. Previous Work • Classification of techniques: Radiation-tolerant design • Device level • M. Takai et al. “Soft error susceptibility and immune structures in dynamic random access memories (DRAM’s) investigated by nuclear microprobes,” IEEE Trans. Nucl. Sci. Feb 1996 • Circuit level • Zhou et. al. “Transistor sizing for radiation hardening,” Proc. Int. Reliability Physics Symp. 2004 • System level • S. Mitra et. al. “Robust system design with built-in soft-error resilience," IEEE Computer Feb 2005 • Redundancy based techniques (TMR) • Hardware redundancy – space dimension • Temporal redundancy – time dimension

7. a b a* b* a b out out a a out a* out a a b b a* b* An inverter CWSP element of an inverter CWSP element of NAND2 NAND2 gate CWSP Element • This paper is based on the use of Code Word State Preserving elements • M. Nicolaidis, “Time redundancy based soft-error tolerance to rescue nanometer technologies,” VLSI Test Symposium, April 1999 • What is a CWSP element and how does it work?

8. How does the CWSP element work? OUT Latch/ FF Comb. block with k logic gates Original Circuit δ δ Comb. block with k-1 logic gates P* CW OUT CWSP of the kth gate Latch/ FF P* P Delay δ P CW (inverter) • Delay of 2δ + DCWSP - Dk in the functional pathwhere DCWSP: delay of the CWSP element Dk : delay of the kth gate t1 t2 t3 • Use only one type of CWSP element, that of an inverter • Reduces speed degradation due to body effect • Avoid the need to have a library of CWSP gates • Need to implement the complement of the combinational function, however..

9. FF OUT D LOGIC FF OUT CW* Modified FF D LOGIC EQGLB OUT D LOGIC clk clk Original Circuit clk Detect a radiation strike 0 EQ EQGLBF EQ FF P* CWSP of the inverter GLB FF 1 EQGLB δ P EQGLBF Calculate the correct value clk_d clk CW* CW CW FF Our Approach – Abstract Level EQGLB Our Approach - Architecture

10. Probability of more than one radiation strike in 2 consecutive cycles is 10-10. This is exploited by introducing the MUX shown clk 0 D OUT P* P CW clk_d EQ EQGLB EQGLB EQGLBF GLB FF X CW* EQGLBF clk Our Approach - Timing δ δ CW* Modified FF OUT EQGLB D clk EQ EQ FF 1 P* CWSP of the inverter EQGLBF δ P clk_d CW CW* CW FF EQGLB

11. 0 1 EQGLBF Our Approach – Circuit details CW* Modified FF EQGLB OUT D LOGIC clk EQ EQGLBF EQ FF P* CWSP of the inverter GLB FF EQGLB δ P clk_d clk CW* CW CW FF EQGLB

12. clk clk clk clk clk EQGLB Our Approach – Circuit details • Circuit level design – Modified FF EQGLB clk D OUT clk CW* clk Modified FF

13. 0 1 EQGLBF CW P* POLY2 POLY2 P P Our Approach – Circuit details • Architecture level design • Show the low-level design for each component CW* Modified FF EQGLB OUT D LOGIC clk EQ EQGLBF EQ FF P* CWSP of the inverter GLB FF EQGLB δ P clk_d clk CW* CW CW FF EQGLB

14. EQGLBF Our Approach – Circuit details • EQ, EQGLB and EQGLBF 0 EQ EQ FF EQGLBF GLB FF OUT 1 CW EQGLB EQGLBF clk_d clk EQGLBF CW 0 EQ FF OUT EQGLB EQGLBF GLB FF CW clk_d clk EQGLBF CW

15. 0 1 EQGLBF Analysis of radiation-hardening • Analyze radiation strikes at various nodes CW* Modified FF EQGLB OUT D LOGIC clk EQ EQGLBF EQ FF P* CWSP of the inverter GLB FF EQGLB δ P clk_d clk CW* CW CW FF EQGLB

16. Maximum glitch width The input of the CWSP element should be stable for at least 2δ to harden against a glitch of size δ on any of the inputs of the CWSP element • DMIN constraint CW* Modified FF OUT EQGLB D clk 0 EQ EQ FF 1 P* CWSP of the inverter EQGLBF δ P clk_d CW CW* CW FF EQ EQGLB

17. CW* Modified FF OUT EQGLB D clk 0 EQ EQ FF 1 P* CWSP of the inverter EQGLBF δ P clk_d CW CW* CW FF EQ EQGLB Maximum glitch width If there is a radiation-strike at the D input of the modified FF, CW* should be ready setup time units before the next positive edge of the system clock ‘clk’ • DMAX constraint

18. Experimental Setup • Circuit simulation is performed in SPICE • 65nm BPTM model card is used • VDD = 1V • VTN = |VTP|= 0.22V • Radiation strike was modeled as current source • Q =100fC ,ta= 200ps and tb= 50ps • Q =150fC ,ta= 200ps and tb= 50ps • LGsynth93 and ISCAS85 benchmark circuits

19. DMIN and DMAX constraints • Using ta= 200ps, tb= 50psFor Q=100fC, δ= 500psFor Q=150fC, δ= 600ps • ∆ = 405ps • For Q=100fC, DMIN ≥1000psFor Q=150fC, DMIN ≥ 1200ps • For Q=100fC, DMAX ≥1405psFor Q=150fC, DMAX ≥ 1605ps • So, any design with DMIN > 1000 and DMAX > 1405 can be protected up to 500ps (for Q=100fC, ta= 200ps and tb= 50ps) • For designs with DMIN < 1000ps and DMAX < 1405ps, protect up to: • Brayton et. al. Delay balancing is done in industrial designs, DMIN = 80% DMAX Gate output voltage (V) time (ns)

20. 0 1 EQGLBF For every flip-flop in the circuit One copy for the entire circuit Area overhead • Area overhead calculation CW* Modified FF EQGLB OUT D LOGIC clk EQ EQ FF P* CWSP of the inverter GLB FF EQGLBF EQGLB δ P clk_d clk CW* CW CW FF EQGLB

21. Delay overhead • Delay for unprotected circuitDMAX + Tsetup + TCO= DMAX + 40ps + 69ps • Delay for the protected circuitDMAX + Tsetup + TCO+ Dinput_load= DMAX + 38ps + 76ps + 6.5ps • Dinput_load is the increase in delay of the combinational circuit output (due to the increased load on the D-input of the modified flip-flop of our design)

22. Experimental Results • Q=150fC, ta= 200ps and tb= 50ps • DMIN ≥ 1200ps, DMAX ≥ 1605ps

23. Experimental Results • Q=100fC, ta= 200ps and tb= 50ps • DMIN ≥1000ps, DMAX ≥ 1405ps

24. Experimental Results • For DMIN < 1000ps and DMAX < 1405ps, protect up to:

25. Conclusions and Future Work • With the proposed approach: • For Q=150fC (100fC), ta= 200ps and tb= 50ps delay overhead 0.51 (0.56)%, area overhead 39.31 (45.34)% • For circuits with DMIN< 1000ps or DMAX < 1405psProtect • Delay overhead < 1%, for high – speed, delay critical applications • Combine the proposed approach with gate sizing • Attenuate glitch width using sizing • Now δ is smaller, DMIN, DMAX smaller as well

26. Thank You !