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CMOS Inverter: Operations, Performance, and Optimization

This chapter focuses on understanding the basic operations of CMOS circuits using inverters, analyzing their performance indices such as speed and power consumption, and optimizing the transistor sizing for speed and energy efficiency.

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CMOS Inverter: Operations, Performance, and Optimization

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  1. Chapter 5 The Inverter April 10, 2003

  2. Objective of This Chapter • Use Inverter to know basic CMOS Circuits Operations • Watch for performance Index such as • Speed (Delay calculation) • Optimal Transistor Sizing for speed and Energy • Power Consumption and Dissipation

  3. V DD V V in out C L The CMOS Inverter: A First Glance

  4. V DD CMOS Inverter N Well PMOS Contacts Out In Metal 1 Polysilicon NMOS GND

  5. Two Inverters Share power and ground Abut cells Connect in Metal Vin Vout Vout Vin

  6. V V DD DD R p V out V out R n V V V 0 = = in DD in CMOS InverterFirst-Order DC Analysis VOL = 0 VOH = VDD

  7. Delay Definitions

  8. t = f(R .C ) pHL on L = 0.69 R C on L CMOS Inverter: Transient Response V V DD DD R p V out V out C L C L R n ln(2)=0.69 V 0 V V = = in DD in (a) Low-to-high (b) High-to-low

  9. Voltage TransferCharacteristic

  10. I Dn V = V +V in DD GS,p I = - I D,n D,p V = V +V out DD DS,p V out I I I Dp Dn Dn V =0 V =0 in in V =1.5 V =1.5 in in V V V DS,p DS,p out V =-1 GSp V =-2.5 GSp V = V +V V = V +V in DD GSp out DD DSp I = - I Dn Dp (Vdd = 2.5V in 0.25um CMOS Process) (Vt = 0.4V as shown in Table 3-2) PMOS Load Lines

  11. CMOS Inverter Load Characteristics

  12. CMOS Inverter VTC VM: Vin = Vout Switching Threshold Voltage

  13. Switching Threshold as a Function of Transistor Ratio NMOS and PMOS are in Saturation Modes For r = 1, and saturated velocity NMOS = 2 PMOS, Wp = 2Wn

  14. (V) V Switching Threshold as a Function of Transistor Ratio 1.8 1.7 1.6 1.5 1.4 1.3 M 1.2 1.1 1 0.9 0.8 0 1 10 10 /W W p n

  15. Simulated VTC

  16. 2.5 2 Good PMOS Bad NMOS 1.5 Nominal (V) out Good NMOS Bad PMOS V 1 0.5 0 0 0.5 1 1.5 2 2.5 V (V) in Impact of Process Variations Good: Smaller oxide thickness, smaller L, higher W, smaller VT

  17. Propagation Delay

  18. V DD PMOS Metal1 Polysilicon NMOS CMOS Inverters 1.2 m m =2l Out In GND

  19. CMOS Inverter Propagation Delay

  20. The Transistor as a Switch

  21. The Transistor as a Switch

  22. The Transistor as a Switch

  23. Transient Response ? tp = 0.69 CL (Reqn+Reqp)/2 tpHL tpLH

  24. Design for Performance • Keep loading capacitances (CL) small • Increase transistor sizes (add CMOS gain) • Watch out for self-loading (for the previous stage)! • Increase VDD (????)  Power consumption??

  25. Delay (speed degrade) as a function of VDD

  26. NMOS/PMOS ratio tpHL tpLH tp b = Wp/Wn (See pp. 204) Fig. 5-18

  27. Device Sizing (for fixed load) Self-loading effect: Intrinsic capacitances dominate (Fig. 5-19)

  28. Inverter Sizing

  29. Inverter Chain In Out CL 1 f1 f2 • If CL is given: • How many stages are needed to minimize the delay? • How to size the inverters? • May need some additional constraints.

  30. Inverter Delay • Minimum length devices, L=0.25mm • Assume that for WP = 2WN =2W • same pull-up and pull-down currents • approx. equal resistances RN = RP • approx. equal rise tpLH and fall tpHL delays • Analyze as an RC network 2W W tpLH = (ln 2) RPCL tpHL = (ln 2) RNCL Delay (D): Load for the next stage:

  31. Inverter with Load Delay RW CL RW Load (CL) tp = kRWCL k is a constant, equal to 0.69 Assumptions: no load  zero delay Wunit = 1

  32. Inverter with Load and Para. Cap. CP = 2Cunit Delay 2W Cint CL W Load CN = Cunit Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint) = Delay (Internal) + Delay (Load)

  33. Delay Formula Cint = gCgin withg 1 f = CL/Cgin- effective fanout R = Runit/W ; Cint =WCunit tp0 = 0.69RunitCunit

  34. Apply to Inverter Chain In Out CL 1 2 N tp = tp1 + tp2 + …+ tpN

  35. Optimal Tapering for Given N • Delay equation has (N-1) unknowns, Cgin,2 – Cgin,N • Minimize the delay, find N - 1 partial derivatives • Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1 • Size of each stage is the geometric mean of two neighbors • Each stage has the same effective fanout (Cout/Cin) • Each stage has the same delay

  36. Optimum Delay and Number of Stages When each stage is sized by f and has same effective fanout f: Effective fanout of each stage: Minimum path delay

  37. Example In Out CL= 8 C1 1 f f2 C1 CL/C1 has to be evenly distributed across N = 3 stages:

  38. Optimum Number of Stages For a given load, CL and given input capacitance Cin Find optimal sizing f For g = 0, f = e, N = lnF

  39. Optimum Effective Fanout f Optimum f for given process defined by g fopt = 3.6 forg=1

  40. Impact of Self-Loading on tp No Self-Loading, g=0 With Self-Loading g=1

  41. Normalized delay function of F

  42. Buffer Design N f tp 1 64 65 2 8 18 3 4 15 4 2.8 15.3 1 64 1 8 64 1 4 64 16 1 64 22.6 8 2.8

  43. Power Dissipation

  44. Where Does Power Go in CMOS?

  45. Vdd Vin Vout C L Dynamic Power Dissipation 2 Energy/transition = C * V L dd 2 Power = Energy/transition * f = C * V * f L dd Not a function of transistor sizes! Need to reduce C , V , and f to reduce power. L dd

  46. Modification for Circuits with Reduced Swing

  47. Node Transition Activity and Power

  48. Transistor Sizing for Minimum Energy • Goal: Minimize Energy of whole circuit • Design parameters: f and VDD • tp tpref of circuit with f=1 and VDD =Vref

  49. Transistor Sizing (2) • Performance Constraint (g=1) • Energy for single Transition

  50. Transistor Sizing (3) VDD=f(f) E/Eref=f(f) F=1 2 5 10 20

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