University of Jordan Computer Engineering Department CPE 439: Computer Design Lab

1. University of JordanComputerEngineering DepartmentCPE 439: Computer Design Lab

2. Lab Information • Home Page: http://www.abandah.com/gheith • References: 1- Patterson and Hennessy. Computer Organization & Design: The Hardware/Software Interface, 2nd ed., Morgan Kaufmann, 1997. 2- Hennessy and Patterson. Computer Architecture: A Quantitative Approach, 3rd ed., Morgan Kaufmann, 2002. 3- S. Palnitkar, Verilog HDL, 2nd Ed., Prentice Hall, 2003.

3. Grading: - Pre-Lab Reports and In-Lab Performance 20% - Post-Lab Reports 20% - Mid-Term Exam 20% - Final Exam 40% • Simulator: Verilogger Pro, from Synapticad INC.

4. Lab Outline • Exp. I1: Overview of Verilog • Exp. I2: Introduction to Verilogger Pro • Exp. 1: 32-Bit ALU • Exp. 2: Register File • Exp. 3: Five-Stage Pipeline Datapath (Arithmetic and Memory Instructions) • Exp. 4: Five-Stage Pipeline Datapath (Adding Flow Control Instructions) • Exp. 5: Five-Stage Pipeline Datapath (Solving Data Hazards) • Exp. 6: Direct-Mapped Instruction Cache

5. Verilog Overview

6. What is Verilog? • It is a Hardware Description Language ( HDL ). • Describe a digital system at several levels: - Switch level. - Gate level. - Register Transfer Level ( RTL ). - Behavioral level. • Two major HDL languages: - Verilog - VHDL

7. Cont. • Verilog is easier to learn and use (It is like the C language). • Introduced in 1985 by (Gateway Design Systems) Now, part of (Cadence Design Systems). • 1990: OVI (Open Verilog International). • 1995: IEEE Standard.

8. Why Use Verilog? • Digital systems are highly complex. schematic is useless (just connectivity, not functionality) • Describe the system at wide ranges of levels of abstraction. • Behavioral Constructs: - Hide implementation details. - Arch. Alternatives through simulations. - Detect design bottlenecks. ( BEFORE DETAILED DESIGN BEGINS ) • Automated Tools compile behavioral models to actual circuits.

9. Lexical Conventions • Close to C / C++. • Comments: // Single line comment /* multiple lines comments */ • Case Sensitive • Keywords: - Reserved. - lower case. - Examples: module, case, initial, always.

10. Numbers: <size>’<base format><number> • Size: No. of bits (optional). • Base format:  b: binary  d : decimal  o : octal  h : hexadecimal (DEFAULT IS DECIMAL) Examples:

11. Identifiers: - start with letter or ( _ ). - a combination of letters, digits, ( $ ), and( _ ). - up to 1024 characters.

12. Program Structure • Verilog describes a system as a set of modules. • Each module has an interface to other modules. • Usually: - Each module is put in a separate file. - One top level module that contains:  Instances of hardware modules. Test data. • Modules can be specified: - Behaviorally. - Structurally. • Modules are different from subroutines in other languages (never called).

13. Physical Data Types • Registers (reg): - store values reg [7:0] A; // 8-bit register reg X; // 1-bit register • Wires ( wire ): - do not store a value - represent physical connections between entities. wire [7:0] A; wire X;

14. reg and wire data objects may have a value of: - 0 : logical zero - 1 : logical one - x : unknown - z : high impedance • Registers are initialized to x at the start of simulation. • Any wire not connected to something has the value x. • How to declare a memory in verilog?

15. Operators Binary Arithmetic Operators:

16. Relational Operators:

17. Logical Operators:

18. Bitwise Operators: Unary Reduction Operators ??

19. Other operators: Concatenation: {A[0], B[1:7]} Shift Left: A = A << 2 ; // right >> Conditional: A = C > D?B + 3:B – 2 ;

20. IF Statement • Similar to C/C++. • Instead of { } , use begin and end. if (A == 4) begin B = 2; end else begin B = 4; end

21. Case Statement • Similar to C/ C++ • No break statements are needed. case ( A ) 1’bz: $display) “A is high impedance“); 1’bx: $display) “A is unknown“); default: $display(“A = %b”, A); endcase

22. Example: NAND Gate module NAND (in1, in2, out); input in1, in2; output out; assign out = ~(in1 & in2) ; // continuous // assignment endmodule

23. AND Gate module AND (in1, in2, out); input in1, in2; output out; wire w1; NAND NAND1(in1, in2, w1); NAND NAND2 (w1, w1, out) ; endmodule

24. Test

25. output

26. 4-to-1 Multiplexor

27. Structural Gate-level model module multiplexor4_1(out, in1, in2, in3, in4, cntrl1, cntrl2); output out; input in1, in2, in3, in4, cntrl1, cntrl2; wire notcntlr1, notcntrl2, w, x, y, z; not (notcntrl1, cntrl1); not (notcntrl2, cntrl2); and (w, in1, notcntrl1, notcntrl2); and (x, in2, notcntrl1, cntrl2); and (y, in3, cntrl1, notcntrl2); and (z, in4, cntrl1, cntrl2); or (out, w, x, y, z); endmodule

28. RTL (dataflow) model module multiplexor4_1(out, in1, in2, in3 ,in4, cntrl1, cntrl2); output out; input in1, in2, in3, in4, cntrl1, cntrl2; assign out = (in1 & ~cntrl1 & ~cntrl2) | (in2 & ~cntrl1 & cntrl2) | (in3 & cntrl1 & ~cntrl2) | (in4 & cntrl1 & cntrl2); endmodule

29. Another RTL model module multiplexor4_1(out, in1, in2, in3, in4, cntrl1, cntrl2); output out; input in1, in2, in3, in4, cntrl1, cntrl2; assign out = cntrl1 ? (cntrl2 ? in4 : in3) : (cntrl2 ? in2 : in1); endmodule

30. Behavioral Model module multiplexor4_1(out, in1, in2, in3, in4, cntrl1, cntrl2); output out; input in1, in2, in3, in4, cntrl1, cntrl2; reg out; always @(in1 or in2 or in3 or in4 or cntrl1 or cntrl2) case ({cntrl1, cntrl2}) 2'b00 : out = in1; 2'b01 : out = in2; 2'b10 : out = in3; 2'b11 : out = in4; endcase endmodule Behavioral code: output out must now be of reg type as it is assigned values in a procedural block.

31. D - Flip Flop module dflipflop (d, clk, reset,q); input d, clk, reset; output q; reg q; always @ (posedge clk or posedge reset) begin if (reset) begin q <= 0; end else begin q <= d; end end endmodule

32. N-bit shift register